Integrated Functions (Continued)
4.1.6 CPU_READ/CPU_WRITE Instructions
destination. Both instructions always transfer 32 bits of
data.
The GXm processor has several internal registers that
control the BLT buffer and power management circuitry in
the dedicated cache subsystem. To avoid adding addi-
tional instructions to read and write these registers, the
GXm processor has a general mechanism to access inter-
nal CPU registers with reasonable performance. The
GXm processor has two special instructions to read and
write CPU registers: CPU_READ and CPU_WRITE. Both
instructions fetch a 32-bit register address from EBX as
shown in Table 4-7 and Table 4-8. CPU_WRITE uses EAX
for the source data, and CPU_READ uses EAX as the
These instructions work by initiating a special I/O transac-
tion where the high address bit is set. This provides a very
large address space for internal CPU registers.
The BLT buffer base registers define the starting physical
addresses of the BLT buffers located within the dedicated
L1 cache. The dedicated cache can be configured for up
to 4 KB, so 12 address bits are required for each base
address.
Table 4-7. CPU-Access Instructions
Syntax
Opcode
Registers
Length
CPU_WRITE
CPU_READ
0F3Ch
0F3Dh
EBX = 32-bit address, EAX = Source
2 bytes
2 bytes
EBX = 32-bit address, EAX = Destination
Table 4-8. Address Map for CPU-Access Registers
Register
EBX Address
Description
L1_BB0_BASE
L1_BB1_BASE
L1_BB0_POINTER
L1_BB1_POINTER
PM_BASE
FFFFFF0Ch
FFFFFF1Ch
FFFFFF2Ch
FFFFFF3Ch
FFFFFF6Ch
FFFFFF7Ch
BLT Buffer 0 base address (see Table 4-4 on page 96).
BLT Buffer 1 base address (see Table 4-4 on page 96).
BLT Buffer 0 pointer address (see Table 4-4 on page 96).
BLT Buffer 1 pointer address (see Table 4-4 on page 96).
Power management base address (see Table 6-3 on page 181).
Power management address mask (see Table 6-3 on page 181).
PM_MASK
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