Integrated Functions (Continued)
Table 4-10. Internal Bus Interface Unit Registers (Continued)
Bit
Name
Description
12:8
7
RSVD
XPD
Reserved: Set to 0.
X-Bus Pipeline Disable: When cleared, the address for the next cycle can be driven on the internal X-
Bus before the completion of the data phase of the current cycle.
6
5
4
GNWS
XNWS
GEA
X-Bus Graphics Pipe No Wait State: Data driven on X-Bus from graphics pipeline:
0 = 1 full clock before X_DSX is asserted
1 = On the same clock in which X_RDY is asserted
X-Bus No Wait State: Data driven on X-Bus from Internal Bus Interface Unit:
0 = 1 full clock before X_DSX is asserted
1 = On the same clock in which X_RDY is asserted
Graphics Enable for A Region: Memory R/W operations for address range A0000h-AFFFFh are
directed to the graphics pipeline: 0 = Disable; 1 = Enable.
(Used for VGA emulation.)
3:0
A0
A0 Region: Region control field for address range A0000h-AFFFFh.
Note: Refer to Table 4-11 for decode.
GX_BASE+8008h-800Bh
BC_XMAP_2 Register (R/W)
Default Value = 00000000h
31:28
27:24
23:20
19:16
15:12
11:8
DC
D8
D4
D0
CC
C8
C4
C0
DC Region: Region control field for address range DC000h to DFFFFh.
D8 Region: Region control field for address range D8000h to DBFFFh.
D4 Region: Region control field for address range D4000h to D7FFFh.
D0 Region: Region control field for address range D0000h to D3FFFh.
CC Region: Region control field for address range CC000h to CFFFFh.
C8 Region: Region control field for address range C8000h to CBFFF.
C4 Region: Region control field for address range C4000h to C7FFFh.
C0 Region: Region control field for address range C0000h to C3FFFh.
7:4
3:0
Note: Refer to Table 4-11 for decode.
GX_BASE+800Ch-800Fh
BC_XMAP_3 Register (R/W)
Default Value = 00000000h
31:28
27:24
23:20
19:16
15:12
11:8
FC
F8
F4
F0
EC
E8
E4
E0
FC Region: Region control field for address range FC000h to FFFFFh.
F8 Region: Region control field for address range F8000h to FBFFFh.
F4 Region: Region control field for address range F4000h to F7FFFh.
F0 Region: Region control field for address range F0000h to F3FFFh.
EC Region: Region control field for address range EC000h to EFFFFh.
E8 Region: Region control field for address range E8000h to EBFFFh.
E4 Region: Region control field for address range E4000h to E7FFFh.
E0 Region: Region control field for address range E0000h to E3FFFh.
7:4
3:0
Note: Refer to Table 4-11 for decode.
Table 4-11. Region-Control-Field Bit Definitions
Bit
Position Function
3
PCI Accessible: The PCI slave can access this memory if this bit is set high and if the appropriate Read or Write Enable
bit is also set high.
2
1
Cache Enable: Caching this region of memory is inhibited if this bit is cleared.
Write Enable: Write operations to this region of memory are allowed if this bit is set high. If this bit is cleared, then write
operations in this region are directed to the PCI master.
0
Read Enable: Read operations to this region of memory are allowed if this bit is set high. If this bit is cleared then read
operations in this region are directed to the PCI master.
Note: If Cache Enable = 1 and Write Enable = 1, the Write Enable determination occurs after the data has passed the cache. Since
the cache does write update, write data will change the cache if the address is cached. If a read then occurs to that address.
the data will come from the written data that is in the cache even though the address is not writable. If this must be avoided
then do not make the region cacheable.
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