Integrated Functions (Continued)
4.1.5 Display Driver Instructions
The GXm processor has four instructions to access pro-
cessor core registers. Table 4-6 shows these instructions.
enable or disable all of the graphics instructions. If the
scratchpad size bits are zero, meaning that none of the
cache is defined as scratchpad, then hardware will
assume that the graphics controller is not being used and
the graphics instructions will be disabled. Any other
scratchpad size will enable all of the new instructions.
Note that the base address of the memory map in the
GCR register can still be set up to allow access to the
memory controller registers.
Adding CPU instructions does not create a compatibility
problem for applications that may depend on receiving
illegal opcode traps. The solution is to make these instruc-
tions generate an illegal opcode trap unless a compatibil-
ity bit is explicitly set. The GXm processor uses the
scratchpad size field (bits [3:2] in GCR, Index B8h) to
Table 4-6. Display Driver Instructions
Syntax
Opcode
Description
BB0_RESET
BB1_RESET
CPU_WRITE
CPU_READ
0F3A
0F3B
0F3C
0F3D
Reset the BLT Buffer 0 pointer to the base.
Reset the BLT Buffer 1 pointer to the base.
Write data to CPU internal register.
Read data from CPU internal register.
www.national.com
98
Revision 3.1
NSC [ National Semiconductor ]
