Signal Definitions (Continued)
2.2.2 PCI Interface Signals (Continued)
BGA
SPGA
Signal Name
Pin No.
Pin No
Type
Description
LOCK#
B11
B16
s/t/s
Lock Operation
(PU)
(PU)
LOCK# indicates an atomic operation that may require multiple
transactions to complete. When LOCK# is asserted, nonexclu-
sive transactions may proceed to an address that is not currently
locked (at least 16 bytes must be locked). A grant to start a trans-
action on PCI does not guarantee control of LOCK#. Control of
LOCK# is obtained under its own protocol in conjunction with
GNT#. It is possible for different agents to use PCI while a single
master retains ownership of LOCK#. The arbiter can implement
a complete system lock. In this mode, if LOCK# is active, no
other master can gain access to the system until the LOCK# is
deasserted.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
DEVSEL#
A9
E15
s/t/s
Device Select
(PU)
(PU)
DEVSEL# indicates that the driving device has decoded its
address as the target of the current access. As an input,
DEVSEL# indicates whether any device on the bus has been
selected. DEVSEL# will also be driven by any agent that has the
ability to accept cycles on a subtractive decode basis. As a mas-
ter, if no DEVSEL# is detected within and up to the subtractive
decode clock, a master abort cycle will result except for special
cycles which do not expect a DEVSEL# returned.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
PERR#
A11
D16
s/t/s
Parity Error
(PU)
(PU)
PERR# is used for the reporting of data parity errors during all
PCI transactions except a Special Cycle. The PERR# line is
driven two SYSCLKs after the data in which the error was
detected, which is one SYSCLK after the PAR that was attached
to the data. The minimum duration of PERR# is one SYSCLK for
each data phase in which a data parity error is detected. PERR#
must be driven high for one SYSCLK before going to TRI-STATE.
A target asserts PERR# on write cycles if it has claimed the
cycle with DEVSEL#. The master asserts PERR# on read
cycles.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
SERR#
C12
A17
OD
System Error
(PU)
(PU)
SERR# may be asserted by any agent for reporting errors other
than PCI parity. The intent is to have the PCI central agent assert
NMI to the processor. When the Parity Enable bit is set in the
Memory Controller Configuration register, SERR# will be
asserted upon detecting a parity error on read operations from
DRAM.
REQ[2:0]#
D3,
H3,
E3
E3,
K2,
E1
I
Request Lines
REQ# indicates to the arbiter that an agent desires use of the
bus. Each master has its own REQ# line. REQ# priorities are
based on the arbitration scheme chosen.
(PU)
(PU)
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
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