欢迎访问ic37.com |
会员登录 免费注册
发布采购

30036-23 参数 Datasheet PDF下载

30036-23图片预览
型号: 30036-23
PDF下载: 下载PDF文件 查看货源
内容描述: 的Geode ™ GXLV处理器系列的低功耗X86集成解决方案 [Geode⑩ GXLV Processor Series Low Power Integrated x86 Solutions]
分类和应用:
文件页数/大小: 247 页 / 4117 K
品牌: NSC [ National Semiconductor ]
 浏览型号30036-23的Datasheet PDF文件第29页浏览型号30036-23的Datasheet PDF文件第30页浏览型号30036-23的Datasheet PDF文件第31页浏览型号30036-23的Datasheet PDF文件第32页浏览型号30036-23的Datasheet PDF文件第34页浏览型号30036-23的Datasheet PDF文件第35页浏览型号30036-23的Datasheet PDF文件第36页浏览型号30036-23的Datasheet PDF文件第37页  
Signal Definitions (Continued)  
2.2.2 PCI Interface Signals  
BGA  
SPGA  
Signal Name  
Pin No.  
Pin No  
Type  
Description  
Frame  
FRAME#  
A8  
C13  
s/t/s  
(PU)  
(PU)  
FRAME# is driven by the current master to indicate the begin-  
ning and duration of an access. FRAME# is asserted to indicate  
a bus transaction is beginning. While FRAME# is asserted, data  
transfers continue. When FRAME# is deasserted, the transac-  
tion is in the final data phase.  
This pin is internally connected to a weak (>20-kohm) pull-up  
resistor.  
IRDY#  
TRDY#  
STOP#  
C9  
(PU)  
D14  
(PU)  
s/t/s  
s/t/s  
s/t/s  
Initiator Ready  
IRDY# is asserted to indicate that the bus master is able to com-  
plete the current data phase of the transaction. IRDY# is used in  
conjunction with TRDY#. A data phase is completed on any  
SYSCLK in which both IRDY# and TRDY# are sampled  
asserted. During a write, IRDY# indicates valid data is present  
on AD[31:0]. During a read, it indicates the master is prepared to  
accept data. Wait cycles are inserted until both IRDY# and  
TRDY# are asserted together.  
This pin is internally connected to a weak (>20-kohm) pull-up  
resistor.  
B9  
(PU)  
B14  
(PU)  
Target Ready  
TRDY# is asserted to indicate that the target agent is able to  
complete the current data phase of the transaction. TRDY# is  
used in conjunction with IRDY#. A data phase is complete on any  
SYSCLK in which both TRDY# and IRDY# are sampled  
asserted. During a read, TRDY# indicates that valid data is  
present on AD[31:0]. During a write, it indicates the target is pre-  
pared to accept data. Wait cycles are inserted until both IRDY#  
and TRDY# are asserted together.  
This pin is internally connected to a weak (>20-kohm) pull-up  
resistor.  
C11  
A15  
Target Stop  
(PU)  
(PU)  
STOP# is asserted to indicate that the current target is request-  
ing the master to stop the current transaction. This signal is used  
with DEVSEL# to indicate retry, disconnect or target abort. If  
STOP# is sampled active while a master, FRAME# will be deas-  
serted and the cycle will be stopped within three SYSCLKs.  
STOP# can be asserted in the following cases:  
A PCI master tries to access memory that has been locked by  
another master. This condition is detected if FRAME# and  
LOCK# are asserted during an address phase.  
The PCI write buffers are full or a previously buffered cycle  
has not completed.  
Read cycles that cross cache line boundaries. This is condi-  
tional based upon the programming of bit 1 in the PCI Control  
Function 2 Register.  
This pin is internally connected to a weak (>20-kohm) pull-up  
resistor.  
Revision 1.1  
33  
www.national.com