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1117I33 参数 Datasheet PDF下载

1117I33图片预览
型号: 1117I33
PDF下载: 下载PDF文件 查看货源
内容描述: 800毫安低压差线性稳压器 [800mA Low-Dropout Linear Regulator]
分类和应用: 稳压器
文件页数/大小: 21 页 / 532 K
品牌: NSC [ National Semiconductor ]
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Typical Performance Characteristics (Continued)  
LM1117-5.0 Line Transient Response  
10091911  
Application Note  
1.0 External Capacitors/Stability  
1.1 Input Bypass Capacitor  
An input capacitor is recommended. A 10µF tantalum on the  
input is a suitable input bypassing for almost all applications.  
1.2 Adjust Terminal Bypass Capacitor  
The adjust terminal can be bypassed to ground with a by-  
pass capacitor (CADJ) to improve ripple rejection. This by-  
pass capacitor prevents ripple from being amplified as the  
output voltage is increased. At any ripple frequency, the  
impedance of the CADJ should be less than R1 to prevent the  
ripple from being amplified:  
<
R1  
1/(2π*fRIPPLE*CADJ  
)
10091917  
The R1 is the resistor between the output and the adjust pin.  
Its value is normally in the range of 100-200. For example,  
FIGURE 1. Basic Adjustable Regulator  
3.0 Load Regulation  
>
with R1 = 124and fRIPPLE = 120Hz, the CADJ should be  
11µF.  
1.3 Output Capacitor  
The LM1117 regulates the voltage that appears between its  
output and ground pins, or between its output and adjust  
pins. In some cases, line resistances can introduce errors to  
the voltage across the load. To obtain the best load regula-  
tion, a few precautions are needed.  
The output capacitor is critical in maintaining regulator sta-  
bility, and must meet the required conditions for both mini-  
mum amount of capacitance and ESR (Equivalent Series  
Resistance). The minimum output capacitance required by  
the LM1117 is 10µF, if a tantalum capacitor is used. Any  
increase of the output capacitance will merely improve the  
loop stability and transient response. The ESR of the output  
capacitor should range between 0.3- 22. In the case of  
the adjustable regulator, when the CADJ is used, a larger  
output capacitance (22µf tantalum) is required.  
Figure 2, shows a typical application using a fixed output  
regulator. The Rt1 and Rt2 are the line resistances. It is  
obvious that the VLOAD is less than the VOUT by the sum of  
the voltage drops along the line resistances. In this case, the  
load regulation seen at the RLOAD would be degraded from  
the data sheet specification. To improve this, the load should  
be tied directly to the output terminal on the positive side and  
directly tied to the ground terminal on the negative side.  
2.0 Output Voltage  
The LM1117 adjustable version develops a 1.25V reference  
voltage, VREF, between the output and the adjust terminal.  
As shown in Figure 1, this voltage is applied across resistor  
R1 to generate a constant current I1. The current IADJ from  
the adjust terminal could introduce error to the output. But  
since it is very small (60µA) compared with the I1 and very  
constant with line and load changes, the error can be ig-  
nored. The constant current I1 then flows through the output  
set resistor R2 and sets the output voltage to the desired  
level.  
For fixed voltage devices, R1 and R2 are integrated inside  
the devices.  
9
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