100336 Low Power 4-Stage Counter/Shift Register
August 1998
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three Select
(S
n
) inputs determine the mode of operation, as shown in the
Function Select table. Two Count Enable (CEP, CET) inputs
are provided for ease of cascading in multistage counters.
One Count Enable (CET) input also doubles as a Serial Data
(D
0
) input for shift-up operation. For shift-down operation, D
3
is the Serial Data input. In counting operations the Terminal
Count (TC) output goes LOW when the counter reaches 15
in the count/up mode or 0 (zero) in the count/down mode. In
the shift modes, the TC output repeats the Q
3
output. The
dual nature of this TC/Q
3
output and the D
0
/CET input
means that one interconnection from one stage to the next
higher stage serves as the link for multistage counting or
shift-up operation. The individual Preset (P
n
) inputs are used
to enter data in parallel or to preset the counter in program-
mable counter applications. A HIGH signal on the Master Re-
set (MR) input overrides all other inputs and asynchronously
clears the flip-flops. In addition, a synchronous clear is pro-
vided, as well as a complement function which synchro-
nously inverts the contents of the flip-flops. All inputs have 50
kΩ pull-down resistors.
Features
n
n
n
n
n
40% power reduction of the 100136
2000V ESD protection
Pin/function compatible with 100136
Voltage compensated operating range = −4.2V to −5.7V
Standard Microcircuit Drawing
(SMD) 5962-9230601
Logic Symbol
Pin
Names
CP
CEP
D
0
/CET
S
0
–S
2
MR
DS100307-1
Description
Clock Pulse Input
Count Enable Parallel Input (Active LOW)
Serial Data Input/Count Enable
Trickle Input (Active LOW)
Select Inputs
Master Reset Input
Preset Inputs
Serial Data Input
Terminal Count Output
Data Outputs
Complementary Data Outputs
P
0
–P
3
D
3
TC
Q
0
–Q
3
Q
0
–Q
3
© 1998 National Semiconductor Corporation
DS100307
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