SM9501A/B
BLOCK DIAGRAM
PON
Bias
OUT
VSS HLDN CP CB
VDD
VDDA
Decoder
Peak/Bottom
Hold Det.
AGC Control
IN1
AGC Amp
Post Amp
Rectifier
LPF
IN3
IN2
FCN
XO VSSA XI
LF
PIN DESCRIPTION
1
2
Number
Name
VDDA
IN1
I/O
A/D
A
Description
1
2
−
I
AGC amplifier (+) supply input
Antenna input 1 (fixed input)
A
3
IN3
I
A
Antenna input 3 (via analog switch)
Antenna input 2 (analog switch bypass)
Analog switch control input (active LOW)
Output for crystal filter
4
IN2
I
A
5
FCN
XO
Ipu
O
D
A
6
7
VSSA
XI
−
A
AGC amplifier (–) supply input
Input from crystal filter
8
I
A
9
LF
O
A
Rectifier LPF capacitor connection
Bottom hold detector capacitor connection
Peak hold detector capacitor connection
AGC gain hold control (active LOW)
Substrate (–) supply input
10
11
12
13
14
15
16
−
CB
O
A
CP
O
A
HLDN
VSS
OUT
PON
VDD
TN
Ipu
−
D
A
O
D
D
A
Clock time code output (active LOW)
Standby state control input (active LOW)
(+) supply input
Ipu
−
Ipu
D
AGC amplifier gain control switch (active LOW, for test mode)
1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin
2. A: analog signal, D: digital signal
NIPPON PRECISION CIRCUITS INC.—3
NPC [ NIPPON PRECISION CIRCUITS INC ]
