SM5843A×1
Data Input to Output Delay Timing
This is the digital filter arithmetic computation time
from the completion of data input at rate fs (t
on the rising edge of LRCI to the start of data output
at rate 8fs (t ) on the falling edge of WCKO.
)
INPUT
OUTPUT
Filter response
CKSLN
SYNCN
Mode
t
− t
OUTPUT INPUT
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
After reset + sync mode
Jitter-free mode
44.625/fs
LOW (256fs)
44.25/fs − 45.0/fs
44.75/fs
Filter response 1
After reset + sync mode
Jitter-free mode
HIGH (384fs)
LOW (256fs)
HIGH (384fs)
44.375/fs − 45.125/fs
25.625/fs
After reset + sync mode
Jitter-free mode
25.25/fs − 26.0/fs
25.75/fs
Filter response 2
After reset + sync mode
Jitter-free mode
25.375/fs − 26.125/fs
1/fs
LRCI
44/fs(Filter Response 1)
25/fs(Filter Response 2)
Serial data Input
tINPUT
WCKO
(256fs)
Serial data output
Serial data output
OUTPUT
tOUTPUT
WCKO
(384fs)
t
Figure 12. Delay timing (SYNCN = LOW)
44.625/fs (Filter Response 1)
25.625/fs (Filter Response 2)
tINPUT
tOUTPUT
tINPUT
tOUTPUT
Figure 13. Delay timing (SYNCN = CKSLN = LOW)
NIPPON PRECISION CIRCUITS—21
NPC [ NIPPON PRECISION CIRCUITS INC ]
