SM5843A×1
Attenuation operation
When an attenuation value DATT is set, the attenua-
tion changes smoothly from the current attenuation
level to the new level. The new attenuation data is
stored in the attenuation register while the current
attenuation data is stored in a temporary register. The
attenuation then changes smoothly by ramping
between the two register values, updating the tempo-
rary register with each step. If a new attenuation
value for DATT is set before the previous target
attenuation level is reached, the attenuation then
ramps toward the new attenuation level.
When MUTE is HIGH, the attenuation level is −∞.
When MUTE goes LOW (muting OFF), the attenua-
tion level returns to that of the original value of
DATT.
Setting1
DATT1
Setting4
DATT4
DATT2
DATT2
(Gain)
DATT3
Setting2
−∞
Setting3
MUTE
L
H
L
Time
Figure 4. Attenuation and mute timing
System Clock (XTI, XTO, CKO, CKSLN)
Two system clock frequencies, 384fs and 256fs, can
be used. An external clock source can be input on
XTI, or a crystal oscillator can be constructed by
connecting a crystal between XTI and XTO. The
system clock is also buffered and then output on
CKO. The system clock frequency selection and the
internal clock frequency are shown in the following
table.
CKSL
Parameter
HIGH
384fs
384fs
LOW
256fs
256fs
XTI input clock frequency (f = 1/t )
XI
XI
CKO clock frequency
Internal clock frequency (t
)
2 × t
t
XI
SYS
XI
to timing controller
CKSLN
XTI
1 / 2
Internal system clock
(192fs or 256fs)
XTO
CKO
Figure 5. Clock generator circuit
NIPPON PRECISION CIRCUITS—16
NPC [ NIPPON PRECISION CIRCUITS INC ]
