5026 series
PAD LAYOUT
(Unit: µm)
(750,850)
VSS
Q
VDD
Y
INHN
XT
NPC
XTN
(0,0)
X
Chip size: 0.75 × 0.85mm
Chip thickness: 180 20ꢀm
PAD size: 90ꢀm
Chip base: V level
DD
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Name
I/O
Description
X
Y
Output state control input. High impedance when LOW (oscillator stops).
Power-saving pull-up resistor built-in.
INHN
I
605
413
XT
I
Amplifier input
579
171
131
144
144
438
Crystal connection pins.
Crystal is connected between XT and XTN.
Amplifier output
XTN
VDD
O
–
Supply voltage
Output. Output frequency determined by internal circuit to one of f , f /2, f /4, f /8, f /16,
O
f /32. High impedance in standby mode
O
O
O
O
O
Q
O
–
131
618
705
718
VSS
Ground
SEIKO NPC CORPORATION —2