SM5006 series
PAD LAYOUT
PINOUT
(Unit: µm)
(Top view)
VDD
Q
(920,1310)
H A 5 0 0 6
VDD
1
2
3
4
8
7
6
5
INHN
Y
XT
NC
NC
Q
XTN
VSS
(0,0)
XT XTN VSS
X
INHN
Chip size: 0.92 × 1.31mm
Chip thickness: 300 30ꢀm
Chip base: V level
DD
PIN DESCRIPTION and PAD DIMENSIONS
Pad dimensions [µm]
Number
Name
I/O
Description
X
Y
212
212
212
212
1152
–
1
2
3
4
5
6
7
8
INHN
XT
I
I
Output state control input. High impedance when LOW. Pull-up resistor built in
195
385
575
766
765
–
Amplifier input.
Crystal oscillator connection pins.
Crystal oscillator connected between XT and XTN
Amplifier output.
XTN
VSS
Q
O
–
O
–
–
–
Ground
Output. Output frequency (f )
O
NC
No connection
No connection
Supply voltage
NC
–
–
VDD
162
1152
BLOCK DIAGRAM
VDD VSS
XTN
XT
R
C
G
G
R
C
D
D
Rf
Q
INHN
SEIKO NPC CORPORATION —3