NJM3517
■ FUNCTIONAL DESCRIPTION
The circuit, NJM3517, is a high performance motor driver, intended to drive a stepper motor in a unipolar, bi-level
way. Bi-level means that during the first time after a phase shift, the voltage across the motor is increased to a
second voltage supply, VSS, in order to obtain a more-rapid rise of current, see figure 25.
The current starts to rise toward a value which is many times greater than the rated winding current. This com-
pensates for the loss in drive current and loss of torque due to the back emf of the motor.
After a short time, tOn, set by the monostable, the bi-level output is switched off and the winding current flows from
the VMM supply, which is chosen for rated winding current. How long this time must be to give any increase in
performance is determined by VSS voltage and motor data, the L/R time-constant.
In a low-voltage system, where high motor performance is needed, it is also possible to double the motor voltage
by adding a few external components, see figure 4.
The time the circuit applies the higher voltage to the motor is controlled by a monostable flip-flop and determined
by the timing components RT and CT.
The circuit can also drive a motor in traditional unipolar way.
An inhibit input (INH) is used to switch off the current completely.
■ LOGIC INPUTS
All inputs are LS-TTL compatible. If any of the logic inputs are left open, the circuit will accept it as a HIGH level.
NJM3517 contains all phase logic necessary to control the motor in a proper way.
STEP — Stepping pulse
One step is generated for each negative edge of the STEP signal. In half-step mode, two pulses will be required to
move one full step. Notice the set up time, ts, of DIR and HSM signals. These signals must be latched during the
negative edge of STEP, see timing diagram, figure 6.
V
V
SS
D3
MM
+ 5V
+
+
+
NJM3517
D2
D1
C
3
C
4
C
5
V
CC
V
SS
16
15
V
CC
R11
R10
PQR
RC 12
13
14
L
L
A
Mono
F - F
CMOS, TTL-LS
Input / Output-Device
B
MOTOR
R
T
C
T
R9 R8
STEP
DIR
7
6
STEP
D3-D6
PA
PB
Phase
Logic
1
2
P
P
B2
CW / CCW
HSM 10
INH 11
B1
HALF / FULL STEP
5
4
P
P
A2
A1
NORMAL /INHIBIT
(Optional Sensor)
O
9
8
A
B
O
D3-D6 are
UF 4001 or
BYV 27
3
GND
Figure 3.
Typical
<
GND
trr 100 ns
GND (V )
CC
GND (V ,V )
MM SS
application
VMM
+ 5V
+
+
R1
NJM3517
D1
C3
C4
VCC
16
VSS
15
VCC
R10
PQR
Q1
Q3
C1
RC 12
13 LA
14 LB
Mono
F - F
CMOS, TTL-LS
Input / Output-Device
RT CT
R9 R8
R2
STEP
DIR
7
6
STEP
1/2 MOTOR
R13
Equal to
Phase A
PA
PB
Phase
Logic
1
2
PB2
PB1
CW / CCW
R12
HSM 10
INH 11
HALF / FULL STEP
R4
R5
5
4
PA2
PA1
Q5
NORMAL /INHIBIT
(Optional Sensor)
OA
OB
9
8
Q6
Figure 4.
Voltage
3
GND
doubling with
external
transistors
GND
GND (VCC
)
GND (VMM,VSS
)
NJRC [ NEW JAPAN RADIO ]
