S Series Multifunction DAQ – up to 16-Bit,
up to 3 MS/s per Channel, up to 8 Analog Inputs
CAL
Mux
Address/Data
DustMITE
PGIA
AI 0
16-Bit
ADC
AI 0
Control
Channel Control 0
PGIA
AI 1
16-Bit
ADC
AI 1
Config
EEPROM
Data (32)
Address (32)
Channel Control 1
PGIA
AI 2
16-Bit
ADC
SCARAB
AI 2
ADC Data
Cal
EEPROM
Channel Control 2
PGIA
AI 3
16-Bit
ADC
AI 3
AI Control
I/O Connector
Channel Control 3
PGIA
AI 4
16-Bit
ADC
AI 4
FPGA
STCA
Channel Control 4
PGIA
AI 5
16-Bit
ADC
AI 5
CPLD
Trigger
Analog
Input
Timing/
Control
DMA/IRQ
DMA/IRQ
PCI/PXI Bus
Channel Control 5
PGIA
AI 6
16-Bit
ADC
AI 6
Counter/
Timing I/O
DAQ-
STC
Analog
Output
Timing/
Control
Bus
Interface
AI 0 -
AI 1 +
AI 1 GND
AI 2 -
AI 3 +
AI 3 GND
AI 4 +
AI 4 GND
Ü
Ü
AI 5 -
AI 6 +
Ü
AI 6 GND
Ü
AI 7 -
Ü
NC
NC
NC
P0.4
D GND
P0.1
P0.6
D GND
+5 V OUTPUT
D GND
D GND
PFI 0/AI START TRIG
Ü
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
AI 0 +
AI 0 GND
AI 1 -
AI 2 +
AI 2 GND
AI 3 -
NC
Ü
AI 4 -
Ü
AI 5 +
AI 5 GND
Ü
AI 6 -
Ü
AI 7 +
Ü
Ü
AI 7 GND
NC
NC
D GND
P0.0
P0.5
D GND
P0.2
P0.7
P0.3
AI HOLD COMP
EXTSTROBE*
D GND
PFI 2/AI CONV CLK*
PFI 3/CTR 1 SOURCE
PFI 4/CTR 1 GATE
CTR 1 OUT
D GND
PFI 7/AI SAMP CLK
PFI 8/CTR 0 SOURCE
D GND
D GND
Digital I/O
Channel Control 6
PGIA
AI 7
16-Bit
ADC
AI 7
FPGA DIO
Analog
Trigger
Circuitry
RTSI Bus
Interface
Channel Control 7
Protection
PFI/Trigger
Timing
Digital I/O
RTSI
Connector
Buffer
STC
Figure 2. PXI-6123 and PXI-6122 Block Diagram (channels 4-7 do not apply to NI 6122)
CAL
Mux
Address/Data
DustMITE
PGIA
AI 0
14-Bit
ADC
AI 0
Control
PFI 1/AI REF TRIG
D GND
+5 V OUTPUT
D GND
PFI 5
PFI 6
D GND
PFI 9/CTR 0 GATE
CTR 0 OUT
FREQ OUT
Channel Control 0
PGIA
AI 1
14-Bit
ADC
AI 1
Config
EEPROM
Data (32)
Address (32)
Channel Control 1
PGIA
AI 2
14-Bit
ADC
SCARAB
AI 2
ADC Data
Cal
EEPROM
Channel Control 2
PGIA
AI 3
14-Bit
ADC
AI 3
AI Control
Channel Control 3
PGIA
AI 4
14-Bit
ADC
AI 4
FPGA
STCA
PXI Edge Connector
I/O Connector
NC = No Connect
Ü
NC on NI 6122
Figure 4. PXI-6123, PXI-6122, PXI-6133,
and PXI-6132 Pinout
Channel Control 4
PGIA
AI 5
14-Bit
ADC
AI 5
CPLD
Trigger
Analog
Input
Timing/
Control
DMA/IRQ
DMA/IRQ
Channel Control 5
PGIA
AI 6
14-Bit
ADC
AI 6
Counter/
Timing I/O
DAQ-
STC
Analog
Output
Timing/
Control
Bus
Interface
Digital I/O
Channel Control 6
PGIA
AI 7
14-Bit
ADC
AI 7
FPGA DIO
Analog
Trigger
Circuitry
RTSI Bus
Interface
Channel Control 7
Protection
PFI/Trigger
Timing
Digital I/O
RTSI
Connector
Buffer
STC
Figure 3. PXI-6133 and PXI-6132 Block Diagram (channels 4-7 do not apply to NI 6132)
4
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