S Series Multifunction DAQ – up to 16-Bit,
up to 3 MS/s per Channel, up to 8 Analog Inputs
CAL
Mux
Address/Data
DustMITE
AI 0
16-Bit
ADC
Control
AI 0
AI 1
AI 2
AI 3
AI 4
AI 5
AI 6
AI 7
PGIA
Channel Control 0
Data (32)
Address (32)
AI 1
16-Bit
ADC
Config
EEPROM
PGIA
Channel Control 1
SCARAB
AI 2
16-Bit
ADC
Cal
EEPROM
PGIA
Channel Control 2
AI Control
AI 3
16-Bit
ADC
PGIA
Channel Control 3
FPGA
AI 4
16-Bit
ADC
STCA
PGIA
Channel Control 4
DMA/IRQ
AI 5
16-Bit
ADC
CPLD
Analog
PGIA
Input
Timing/
Control
Trigger
DMA/IRQ
34 68
33 67
32 66
31 65
30 64
29 63
28 62
27 61
26 60
25 59
24 58
23 57
22 56
21 55
20 54
19 53
18 52
17 51
16 50
15 49
14 48
13 47
12 46
11 45
10 44
AI 0 -
AI 1 +
AI 0 +
Channel Control 5
DAQ-
STC
Counter/
Timing I/O
Bus
AI 0 GND
AI 1 -
Interface
AI 6
16-Bit
ADC
PGIA
AI 1 GND
AI 2 -
Analog
Output
Timing/
Control
RTSI Bus
Interface
Digital I/O
AI 2 +
Channel Control 6
AI 3 +
AI 2 GND
AI 3 -
AI 7
16-Bit
ADC
Analog
Trigger
Circuitry
AI 3 GND
AI 4 + Ü
PGIA
NC
RTSI
Connector
AI 4 GND Ü
AI 5 - Ü
AI 4 - Ü
Channel Control 7
PFI/Trigger
Timing
AI 5 + Ü
AI 6 + Ü
AI 5 GND Ü
AI 6 - Ü
Buffer
AI 6 GND Ü
AI 7 - Ü
Digital I/O
STC
AI 7 + Ü
NC
AI 7 GND Ü
NC
NC
NC
NC
Figure 2. PXI-6123 and PXI-6122 Block Diagram (channels 4-7 do not apply to NI 6122)
P0.4
D GND
D GND
P0.0
P0.1
P0.5
P0.6
D GND
D GND
P0.2
+5 V OUTPUT
D GND
P0.7
P0.3
D GND
AI HOLD COMP
EXTSTROBE*
D GND
PFI 0/AI START TRIG
PFI 1/AI REF TRIG
D GND
CAL
Mux
Address/Data
9
8
7
6
5
4
3
2
1
43
42
41
40
39
38
37
36
35
PFI 2/AI CONV CLK*
PFI 3/CTR 1 SOURCE
PFI 4/CTR 1 GATE
CTR 1 OUT
D GND
DustMITE
AI 0
14-Bit
ADC
Control
+5 V OUTPUT
D GND
AI 0
AI 1
AI 2
AI 3
AI 4
AI 5
AI 6
AI 7
PGIA
PFI 5
Channel Control 0
Data (32)
Address (32)
PFI 6
AI 1
14-Bit
ADC
Config
PGIA
EEPROM
D GND
PFI 7/AI SAMP CLK
PFI 8/CTR 0 SOURCE
D GND
PFI 9/CTR 0 GATE
CTR 0 OUT
FREQ OUT
Channel Control 1
SCARAB
AI 2
14-Bit
ADC
Cal
EEPROM
PGIA
D GND
Channel Control 2
AI Control
AI 3
14-Bit
ADC
NC = No Connect
Ü NC on NI 6122
PGIA
Channel Control 3
FPGA
AI 4
14-Bit
ADC
STCA
PGIA
Figure 4. PXI-6123, PXI-6122, PXI-6133,
and PXI-6132 Pinout
Channel Control 4
DMA/IRQ
AI 5
14-Bit
ADC
CPLD
Analog
Input
Timing/
Control
PGIA
Trigger
DMA/IRQ
Channel Control 5
DAQ-
STC
Counter/
Timing I/O
Bus
Interface
AI 6
14-Bit
ADC
PGIA
Analog
Output
Timing/
Control
RTSI Bus
Interface
Digital I/O
Channel Control 6
AI 7
14-Bit
ADC
Analog
Trigger
Circuitry
PGIA
RTSI
Connector
Channel Control 7
PFI/Trigger
Timing
Buffer
Digital I/O
STC
Figure 3. PXI-6133 and PXI-6132 Block Diagram (channels 4-7 do not apply to NI 6132)
4
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