IEEE 488.2 Controller Chip
Source Handshake
Response to ATN
Limits (ns)
Symbol Min Max
Test
Condition
Limits (ns)
Test
Parameter
Parameter
ATN ↑ to NRFD↓
Symbol
Min
Max
Condition
Acceptorhandshake
holdoff
t
35
NDAC↑ to DAV↑
t
–
–
40
40
–
AF
ND
NDAC↑ to INT↓ or ACCRQ↓
t
INT(DOIE Bit=1)
ACCGR (DMAO Bit=1)
2 µs T1, 5MHz
1.1 µs T1, 5MHz
500 ns T1, 5MHz
350 ns T1, 5MHz
NI
ATN↓ to NDAC↓
ATN↓ to TE↓
t
35
30
AIDS→ANRS
AN
t
TACS→TADS
AT
WE↑ to DAV↓
WE↑ to DAV↓
WE↑ to DAV↓
WE↑ to DAV↓
t
2000 2180
1200 1380
WD
t
WD
t
600
400
780
580
WD
t
ATN
WD
tAT
TE
WE
t
AN
NDAC
NRFD
t
AF
D7-0
tNI
INT/ACCGR
Figure 11. ATN Response Timing
DIO 8-1
tWD
Parallel Poll
DAV
tND
Limits (ns)
Min Max
Test
NDAC
Parameter
Symbol
tED
tET
Condition
EOI↓ to DIO↓ valid
EOI↓ to TE↑
EOI↑ to TE↓
90
30
30
PPSS →PPAS
PPSS →PPAS
PPAS →PPSS
Figure 9. Source Handshake Timing
tTE
Acceptor Handshake
Limits (ns)
Test
Condition
ATN
EOI
TE
Parameter
Symbol Min
Max
35+3T
25
DAV
DAV
DAV
↓
↑
↓
to NDAC↑
to NDAC
to INT
t
DD
↓
t
DF
t
TE
↓
or ACCRQ
↓
t
50+2T INT(DIIE Bit=1),
ACCGR (DMAI Bit=1)
20
DI
tET
DAV↓
to NRFD
↓
t
DR
t
ED
DIO
DBIN↑ to NRFD↑
t
35
Read of DIR, not in
NR
Holdoff state
Figure 12. Parallel Poll Response Timing
Note: T = one clock period
DAV
tDF
t
DD
NDAC
NRFD
t
DR
tNR
tDI
INT/ACCRQ
DBIN
Figure 10. Acceptor Handshake Timing
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8
NI [ National Instruments ]
