IEEE 488.2 Controller Chip
Pin Number
PLCC
43
DIP
39
30
40
20
–
QFP
4
Mnemonic
TR
Type
Description
†
O
Trigger asserts when one of the trigger conditions is satisfied.
Controller asserts when the NAT9914 is Controller-In-Charge.
Power pin – +5 V ( 5ꢀ)
†
33
38
CONT*
VDD
O
44
5
–
–
–
22
27
VSS
Ground pin – 0 V
1, 18,
28,40
1, 6,
23, 33
NC
No connect
OC= Open collector.
† The pin contains an internal pull-up resistor of 25 kΩ to 100 kΩ.
* Active low.
†† In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with a 4.7 kΩ resistor.
††† RS0 and RS1 contain an internal pull-up resistor of 25 kΩ to 100 kΩ. RS2 does not contain an internal pull-up or pull-down resistor.
D(7-0)
CE*
Data-In
DIO(8-1)*
RS(2-0)
DBIN
Command Pass Through
Command/Data Out
Address Status
Message
Decoder
Read/
Write
Control
WE*
ACCRQ*
ACCGR*
Interface
Functions
SH1
AH1
CONT*
TE
Address Mode
TR
T5/TE5
Address
L3/LE3
SR1
End-of-String
Interrupt Mask 0, 1, 2
RL1
PP1/PP2
DC1
Interrupt Status 0, 1, 2
INT*
CLK
DT1
Internal Count
Internal Count 2
C1-C5
RSV Gen
EOI Gen
Serial Poll
Parallel Poll
Aux A, B, E, F, G, I
SASR
STB Out
SYNC
Auxiliary
Command Decoder
RESET*
GPIB
Control
Bus Status
and Control
Version
Figure 4. NAT9914 Block Diagram
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4
NI [ National Instruments ]
