IEEE 488.2 Controller Chip
Pin Identication
Pin Number
PLCC
11, 12, 13,
14, 15, 16,
17, 19
4
DIP
10, 11, 12,
13, 14, 15,
16, 17
3
QFP
16, 17, 18,
19, 20, 21,
22, 24
9
Mnemonic
D(7-0)
Type
I/O
†
Description
Bidirectional 3-state data bus transfers
comma
n
ds, data, a
n
d stat
u
s betwee
n
the
NAT9914 a
n
d the CPU.
D0 is the most significant bit.
Chip Enable gives access to the
register
selected by a
read
or write operation, and the
register
selects RS(2-0).
With the Data Bus Input, you can place the
contents of the
register
selected by RS(2-0)
and CE* onto the data bus D(7-0). The polarity
of DBIN is
reversed
for DMA operation.
The Write input latches the contents of the
data bus D(7-0) into the
register
selected by
RS(2-0).
CE*
I
6
5
11
DBIN
I
†
5
4
10
WE*
I
3
2
20
21
10
2
1
18
19
9
8
7
25
26
15
ACCGR*
ACCRQ*
CLK
RESET*
INT*
(OC)
I
†
O
I
†
The Access Grant signal selects the DIR or
CDOR for the current
read
or write cycle.
The Access Request output asserts to
request
a DMA Acknowledge cycle.
The CLK input can be
up
to 20 MHz.
Asserting the RESET* input places the
NAT9914 in an initial, idle state.
The Interrupt output asserts when one of the
unmasked
interrupt conditions is true. The
NAT9914 does
not
drive INT* high. The INT*
pin must be pulled
up
by an external
resistor.
The Register
Selects
determine which
register
to access during a
read
or write operation.
Bidirectional control line initializes the
IEEE 488 interface functions.
Bidirectional control line selects either
remote
or local control of devices.
Bidirectional control line indicates whether
data on the DIO lines is an interface or device-
dependent message.
Bidirectional control line
requests
service from
the controller.
8-bit bidirectional IEEE 488 data bus
I
†
O
9, 8, 7
25
24
31
8, 7, 6
23
22
28
14, 13, 12
30
29
36
RS(2-0)
IFC*
REN*
ATN*
I
†††
I/O
,
(OC)
† ††
I/O
(OC)
I/O
†
†
32
34, 35, 36,
37, 38, 39,
41, 42
29
27
26
30
23
29
31, 32, 33,
34, 35, 36
37, 38
26
25
24
27
21
37
39, 40, 41,
42, 43, 44,
2, 3
34
32
31
35
28
SRQ*
DIO(8-1)*
I/O
†
I/O
†
DAV*
NRFD*
NDAC*
EOI*
TE
I/O
†
Handshake line indicates that the data on the
DIO(8-1)* lines is valid.
Handshake line indicates that the device is
ready
for data.
Handshake line indicates the completion of a
message
reception.
Bidirectional control line indicates the last byte
of a data message or executes a parallel poll.
Talk Enable controls the direction of the
IEEE 488 data transceiver.
I/O
I/O
I/O
O
†
†
†
†
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3
NI [ NATIONAL INSTRUMENTS CORPORATION ]
