NAT9914APD
NAT9914APL
9914 Mode Registers
In 9914 mode, the NAT9914 registers
consist of all the TI TMS9914A registers and
two types of additional registers – newly
defined registers and paged-in registers. The
NAT9914 maps the newly defined registers
into the unused portion of the 9914 address
space. Each paged-in register appears at offset
2 immediately after you issue an auxiliary
page-in command, and it remains there until
you page another register into the same space
or you issue a reset. The table below lists all
the registers in the 9914 register set.
9914 Register Set
Register
Interrupt Status 0
Interrupt Mask 0
Interrupt Status 1
Interrupt Mask 1
Address Status
Interrupt Mask 2
†
End-of-String
†
Bus Control
†
Accessory
†
Bus Status
Auxiliary Command
Interrupt Status 2
†
Address
Serial Poll Status
†
Serial Poll Mode
Command Pass Thru
Parallel Poll
Data-In
Data-In
Page In
U
U
U
U
U
P
P
P
P
U
U
P
U
P
U
U
U
U
U
RS(2-0)
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
XXX
WE*
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
X
DBIN
1
0
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
CE*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
ACCGR*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Data Registers
Data In Register (DIR)
DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01
Interrupt Mask Register 0 (IMR0)
DMAO
†
DMAI
†
BI
IE
BO END SPAS RLC MAC
IE
IE
IE
IE
IE
Command/Data Out Register (CDOR)
DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01
Interrupt Mask Register 1 (IMR1)
GET
IE
ERR UNC APT DCAS MA
IE
IE
IE
IE
IE
SRQ
IE
IFC
IE
The data registers transfer data and
commands between the IEEE 488 bus and
the CPU. The Data In Register (DIR) holds
data sent from the GPIB to the CPU, and
the CDOR holds information to transfer
onto the IEEE 488 bus.
Interrupt Mask Register 2 (IMR2)
†
GLINT STBO NLEN 0
IE
LLOC ATNI
IE
IE
0
CIC
IE
The interrupt registers consist of interrupt
status bits, interrupt mask bits, and some
noninterrupt-related bits. Several conditions
can cause an interrupt. The interrupt status
sets if its condition is true and an interrupt is
generated if you set the corresponding mask
bit. Most interrupt status bits are cleared
when read. The following tables list the
individual bits in the interrupt registers,
along with descriptions.
Interrupt Status and/or Mask
Register Bits
Bits
INT0
INT1
BI
BO
END
SPAS
RLC
MAC
GET
ERR
UNC
APT
DCAS
MA
SRQ
IFC
STBO
†
LLOC
†
ATNI
†
CIC
†
GLINT
†
Description
OR of all unmasked ISR0 bits
OR of all unmasked ISR1 bits
Byte In
Byte Out
END (EOI or EOS message received)
SPAS (Serial Poll Active State)
Remote/Local Change
My Address Change
Group Execute Trigger
Data Transmission Error
Unrecognized Command
Address Pass Through
Device Clear Active State
My Address
Service Request (SRQ) asserted
Interface Clear (IFC) asserted
Status Byte Out Request
Lockout State Change
Attention (ATN) asserted
Controller-In-Charge
Global Interrupt Enable
Command/Data Out
U
1 1 1
0
0
0
1
Command/Data Out
U
XXX
0
1
X
0
The '†' symbol denotes features (such as registers and auxiliary commands) that are not available in
the TMS9914A.
Notes for the PAGE-IN column
U = Page-in auxiliary commands do not
affect the register offset.
P = The register offset is valid only after a
page-in auxiliary command.
Interrupt Registers
Interrupt Status Register 0 (ISR0)
INT0 INT1
BI
BO
END SPAS RLC MAC
Interrupt Status Register 1 (ISR1)
GET ERR UNC APT DCAS MA
SRQ
IFC
Interrupt Status Register 2 (ISR2)
†
nba STBO NL
EOS LLOC ATNI
X
CIC
4
N
ATIONAL
I
NSTRUMENTS
NI [ NATIONAL INSTRUMENTS CORPORATION ]
