NAT9914APD
NAT9914APL
Pin Identification
Pin No.
Mnemonic
PLCC
DIP
11, 12, 13, 10, 11, 12, D(7-0)
14, 15, 16, 13, 14, 15,
17, 19
16, 17
4
3
CE*
I
Type
I/O
†
Description
Bidirectional 3-state data bus transfers
commands, data, and status between the
NAT9914 and the CPU. D0 is the most
significant bit.
Chip Enable gives access to the register
selected by a read or write operation, and the
register selects RS(2-0)
With the Data Bus Input, you can place the
contents of the register selected by RS(2-0) and
CE* onto the data bus D(7-0). The polarity of
DBIN is reversed for DMA operation.
The Write input latches the contents of the data
bus D(7-0) into the register selected by RS(2-0)
The Access Grant signal selects the DIR or
CDOR for the current read or write cycle
The Access Request output asserts to request a
DMA Acknowledge cycle
The CLK input can be up to 20 MHz
Asserting the RESET* input places the NAT9914
in an initial, idle state
The Interrupt output asserts when one of the
unmasked interrupt conditions is true. The NAT9914
does not drive INT* high. The INT* pin must be
pulled up by an external resistor.
9, 8, 7
25
24
31
8, 7, 6
23
22
28
RS(2-0)
IFC*
REN*
ATN*
I
†
The Register Selects determine which register to
access during a read or write operation
interface functions
Bidirectional control line selects either remote or
local control of devices
Bidirectional control line indicates whether data
on the DIO lines is an interface or device-
dependent message
32
29
SRQ*
I/O
†
I/O
†
Bidirectional control line requests service from
the controller
8-bit bidirectional IEEE 488 data bus
ACCRQ
ACCGR
CE
WE
DBIN
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
D0
CLK
RESET
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
TR
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
NRFD
NDAC
IFC
REN
TE
NAT9914APD
6
5
DBIN
I
†
Figure 1. NAT9914APD Pin Configuration
DBIN
WE
CE
ACCGR
ACCRQ
NC
VDD
TR
DIO1
DIO2
NC
5
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
CONT
SRQ
ATN
EOI
DAV
4
2
1
18
19
9
WE*
ACCGR*
ACCRQ*
CLK
RESET*
INT*
I
†
I
†
O
I
†
I
†
0
(0C)
RS0
RS1
RS2
INT
D7
D6
D5
D4
D3
D2
D1
6 5 4 3 2 1 44 43 42 41 40
7
39
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
3
2
20
21
10
NAT9914APL
Figure 2. NAT9914APL Pin Configuration
NC
D0
CLK
RESET
VSS
TE
REN
IFC
NDAC
NRFD
NC
I/O
†, ††
Bidirectional control line initializes the IEEE 488
(OC)
I/O
†
(OC)
I/O
†
34, 35, 36, 31, 32, 33, DIO(8-1)*
37, 38, 39, 34, 35, 36
41, 42
37, 38
29
26
DAV*
27
26
30
23
25
24
27
21
NRFD*
NDAC*
EOI*
TE
I/O
†
I/O
†
I/O
†
I/O
†
O
†
Handshake line indicates that the data on the
DIO(8-1)* lines is valid
Handshake line indicates that the device is ready
for data
Handshake line indicates the completion of a
message reception
Bidirectional control line indicates the last byte of
a data message or executes a parallel poll
Talk Enable controls the direction of the IEEE 488
data transceiver
2
N
ATIONAL
I
NSTRUMENTS
NI [ NATIONAL INSTRUMENTS CORPORATION ]
