NAT9914APD
NAT9914APL
Pin No.
PLCC
43
33
44
22
1, 18, 28,
40
OC= Open collector.
†
The pin contains an internal pull-up resistor of 25 kΩ to 100 kΩ.
* Active low.
††
In controller applications where the CLK signal frequency is > 8 MHz, IFC* should be pulled up with
a 4.7 kΩ resistor.
Mnemonic
DIP
39
30
40
20
–
TR
CONT*
VDD
VSS
NC
Type
O
†
O
†
–
–
–
Description
Trigger asserts when one of the trigger conditions
is satisfied
Controller asserts when the NAT9914 is
Controller-In-Charge
Power pin – +5 V (±5%)
Ground pin – 0 V
No connect
D(7-0)
CE*
RS(2-0)
DBIN
WE*
ACCRQ*
ACCGR*
Read/
Write
Control
Data-In
DIO(8-1)*
Command Pass Through
Message
Decoder
Command/Data Out
Interface
Functions
SH1
Address Mode
AH1
T5/TE5
L3/LE3
End-Of-String
Compare
SR1
RL1
PP1/PP2
Interrupt Status 0, 1, 2
Compare
CONT*
TE
TR
Address Status
Address
Interrupt Mask 0, 1, 2
INT*
CLK
Internal Count
Internal Count 2
DC1
DT1
C1-C5
Serial Poll
RSV Gen
Parallel Poll
EOI Gen
Aux A, B, E, F, G, I
STB Out
SYNC
SASR
RESET*
Auxiliary
Command Decoder
Bus Status
and Control
Version
GPIB
Control
Figure 3. NAT9914 Block Diagram
N
ATIONAL
I
NSTRUMENTS
3
NI [ NATIONAL INSTRUMENTS CORPORATION ]
