µPD75216A
t
CY VS
V
DD
*
1. CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator,
the system clock control register (SCC) and the
processor clock control register (PCC). The cycle
time tCY characteristics for power supply voltage
VDD when the main system clock is in operation is
shown below.
(Main System Clock in Operation)
40
32
30
6
5
Operation Guaranteed
Range
2. 2tCY or 128/fXX is set by interrupt mode register
(IM0) setting.
4
3
µ
2
1
0.5
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
54
NEC [ NEC ]
