µPD75216A
No. of Machine
Addressing
Area
Skip
Condition
Note Mnemonic
Operands
mem.bit
Operation
(mem.bit)←1
Bytes
Cycle
SET1
2
2
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*3
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*4
*5
*1
*6
fmem.bit
2
2
(fmem.bit)←1
pmem.@L
2
2
(pmem7–2+L3–2.bit(L1–0))←1
(H+mem3–0.bit)←1
@H + mem.bit
mem.bit
2
2
2
2
(mem.bit)←0
CLR1
SKT
SKF
fmem.bit
2
2
(fmem.bit)←0
pmem.@L
2
2
(pmem7–2+L3–2.bit(L1–0))←0
(H+mem3–0.bit)←0
@H+mem.bit
mem.bit
2
2
2
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2 + S
2
Skip if (mem.bit) = 1
(mem.bit) = 1
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit) = 1
(mem.bit) = 0
(fmem.bit) = 0
(pmem.@L) = 0
(@H+mem.bit) = 0
(fmem.bit) = 1
(pmem.@L) = 1
(@H+mem.bit)=1
fmem.bit
2
Skip if (fmem.bit) = 1
pmem.@L
2
Skip if (pmem7–2+L3–2.bit(L1–0)) = 1
Skip if (H+mem3–0.bit) = 1
Skip if (mem.bit) = 0
@H+mem.bit
mem.bit
2
2
fmem.bit
2
Skip if (fmem.bit) = 0
pmem.@L
2
Skip if (pmem7–2+L3–2.bit(L1–0)) = 0
Skip if (H+mem3–0.bit) = 0
Skip if (fmem.bit) = 1 and clear
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
Skip if (H+mem3–0.bit)=1 and clear
CY←CY (fmem.bit)
@H+mem.bit
fmem.bit
2
SKTCLR
AND1
OR1
2
pmem.@L
2
@H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
CY, fmem.bit
CY, pmem.@L
CY, @H+mem.bit
addr
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))
CY←CY (H+mem3–0.bit)
CY←CY (fmem.bit)
2
2
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))
CY←CY (H+mem3–0.bit)
CY←CY (fmem.bit)
2
2
XOR1
BR
2
2
2
2
CY←CY (pmem7–2+L3–2.bit(L1–0))
CY←CY (H+mem3–0.bit)
2
2
—
—
PC13–0←addr
(Optimum instruction is
selected from among BR !addr,
BRCB !caddr and BR $addr by an
assembler.)
!addr
$addr
!caddr
PCDE
PCXA
3
1
2
2
2
3
2
2
3
3
PC13–0←addr
*6
*7
*8
PC13–0←addr
BRCB
BR
PC13–0←PC13,12+caddr11–0
PC13–0←PC13–8+DE
PC13–0←PC13–8+XA
Note Instruction Group
40
NEC [ NEC ]
