Fig 5-7 Serial Interface Block Diagram
Internal Bus
8
SET1 *2
8
8
P03/SI
SIO0
SIO7
SIO
SIOM
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
Shift Register (8)
*1
SO Output
Latch
P02/SO
INTSIO
IRQSIO
Overflow
Serial Clock
Counter (3)
Set Signal
IRQSIO
Clear Signal
Clear
Serial Start
P01/SCK
R
S
Q
Φ
f
f
xx/24
MPX
xx/210
µ
*
1. CMOS output and N-ch open drain output switchable output buffer.
2. Instruction execution