CHAPTER 2 PIN FUNCTIONS
(12) PCS0 to PCS7 (port CS) ... I/O
Port CS is an 8-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as a port, PCS0 to PCS7 can also be used for chip select signal output when the
memory is expanded externally in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CS mode control register (PMCCS).
(a) Port mode
PCS0 to PCS7 can be set to input or output in 1-bit units by the port CS mode register (PMCS).
(b) Control mode
PCS0 to PCS7 can be set to the port mode or control mode in 1-bit units by the PMCCS register.
(i) CS0 to CS3 (chip select) ... Output
These are the chip select signals for external memory and external peripheral I/Os.
Signal CSn is allocated to memory block n (n = 0 to 3).
These pins become active when a bus cycle for accessing the corresponding memory block is
started.
In the idle state (TI), these pins are inactive.
(13) PCT0 to PCT7 (port CT) ... I/O
Port CT is an 8-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as a port, PCT0 to PCT7 can also be used for control signal output when the memory
is expanded externally in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CT mode control register (PMCCT).
(a) Port mode
PCT0 to PCT7 can be set to input or output in 1-bit units by the port CT mode register (PMCT).
(b) Control mode
PCT0 to PCT7 can be set to the port mode or control mode in 1-bit units by the PMCCT register.
(i) WR0 (lower byte write strobe) ... Output
This is the write strobe signal output pin for the lower data of the external 16-bit data bus.
(ii) WR1 (upper byte write strobe) ... Output
This is the write strobe signal output pin for the higher data of the external 16-bit data bus.
(iii) RD (read strobe) ... Output
This is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for
the external memory or external peripheral I/O. In the idle state (TI), this pin is inactive.
(iv) ASTB (address strobe) ... Output
This is the latch strobe signal output pin for the external address bus.
The output becomes low level in synchronization with the falling edge of the clock in the T1 state of
the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the T3
state.
User’s Manual U15862EJ3V0UD
90
NEC [ NEC ]
