CHAPTER 2 PIN FUNCTIONS
(10) PCD0 to PCD3 (port CD) ... I/O
Port CD is a 4-bit I/O port for which input and output can be set in 1-bit units.
PCD0 to PCD3 operate as an I/O port.
(a) Port mode
PCD0 to PCD3 can be set to input or output in 1-bit units by the port CD mode register (PMCD).
(11) PCM0 to PCM5 (port CM) ... I/O
Port CM is a 6-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as an I/O port, PCM0 to PCM5 can also be used for wait insertion signal input,
internal system clock output, and bus hold control signal I/O in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CM mode control register (PMCCM).
(a) Port mode
PCM0 to PCM5 can be set to input or output in 1-bit units by the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM5 can be set to the port mode or control mode in 1-bit units by the PMCCM register.
(i) WAIT (wait) ... Input
This is a control signal input pin that inserts data waits in a bus cycle. This pin supports
asynchronous input for CLKOUT. In the multiplex mode, sampling starts at the falling edge of the
CLKOUT signal in the T2 and TW states of the bus cycle. In the separate mode, sampling starts at
the rising edge of the CLKOUT signal in the T1 and TW states of the bus cycle. If the setup/hold
times in the sampling timing are not satisfied, wait insertion may not be performed.
(ii) CLKOUT (clock output) ... Output
This is the internal system clock output pin. Since it is in the port mode during the reset period, output
is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin to the control mode
by the port CM mode control register (PMCCM).
(iii) HLDAK (hold acknowledge) ... Output
This is the output pin for the acknowledge signal that indicates that the V850ES/KJ1 has received a
bus hold request and set the external address/data bus and the strobe pins to high impedance.
When this signal is active, the external address/data bus and the strobe pins are in high impedance,
and the bus mastership is handed to the external bus master.
(iv) HLDRQ (hold request) ... Input
This is the input pin by which an external device requests the V850ES/KJ1 to release the external
address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin
is active, the external address/data bus and strobe pins are set to high impedance either when the
V850ES/KJ1 completes execution of the current bus cycle, or immediately if no bus cycle is being
executed. The HLDAK signal is then made active and the bus is released.
To ensure that the bus hold state is entered, keep the HLDRQ signal active until the HLDAK signal is
output.
User’s Manual U15862EJ3V0UD
89
NEC [ NEC ]
