CHAPTER 2 PIN FUNCTIONS
(ii) CLKOUT (clock output) ... Output
This is the internal system clock output pin. Since it is in the port mode during the reset period, output
is not performed from the CLKOUT pin. To perform CLKOUT output, set this pin to the control mode
with the port CM mode control register (PMCCM).
(iii) HLDAK (hold acknowledge) ... Output
This is the output pin for the acknowledge signal that indicates that the V850ES/KG1 has received a
bus hold request and set the external address/data bus and the strobe pins to high impedance.
When this signal is active, the external address/data bus and the strobe pins are in high impedance,
and the bus mastership is handed to the external bus master.
(iv) HLDRQ (hold request) ... Input
This is the input pin by which an external device requests the V850ES/KG1 to release the external
address/data bus and strobe pins. This pin supports asynchronous input for CLKOUT. When this pin
is active, the external address/data bus and strobe pins are set to high impedance either when the
V850ES/KG1 completes execution of the current bus cycle, or immediately if no bus cycle is being
executed. The HLDAK signal is then made active and the bus is released.
To ensure that the bus hold state is entered, keep the HLDRQ signal active until the HLDAK signal is
output.
(9) PCS0, PCS1 (port CS) ... I/O
Port CS is a 2-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as a port, PCS0 and PCS1 can also be used for chip select signal output when the
memory is expanded externally in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CS mode control register (PMCCS).
(a) Port mode
PCS0 and PCS1 can be set to input or output in 1-bit units by the port CS mode register (PMCS).
(b) Control mode
PCS0 and PCS1 can be set to the port mode or control mode in 1-bit units by the PMCCS register.
(i) CS0, CS1 (chip select) ... Output
These are the chip select signals for external memory and external peripheral I/Os.
Signal CSn is allocated to memory block n (n = 0, 1).
These pins become active when a bus cycle for accessing the corresponding memory block is
started.
In the idle state (TI), these pins are inactive.
(10) PCT0, PCT1, PCT4, PCT6 (port CT) ... I/O
Port CT is a 4-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as a port, PCT0, PCT1, PCT4, and PCT6 can also be used for control signal output
when the memory is expanded externally in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CT mode control register (PMCCT).
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
