CHAPTER 2 PIN FUNCTIONS
(iv) TI020, TI021, TI030, TI031 (timer input) ... Input
These are the external count clock input pins for the 16-bit timer.
(v) TO02, TO03 (timer output) ... Output
These are the pulse signal output pins for the 16-bit timer.
(vi) TI51 (timer input) ... Input
This is the external count clock input pin for the 8-bit timer.
(vii) TO51 (timer output) ... Output
This is the pulse signal output pin for the 8-bit timer.
(viii) SO01, SOA1 (serial output) ... Output
These are the serial transmit data output pins for CSI01 and CSIA1.
(ix) SI01, SIA1 (serial input) ... Input
These are the serial receive data input pins for CSI01 and CSIA1.
(x) CSK01, SCKA1 (serial clock) ... I/O
These are the serial clock I/O pins for CSI01 and CSIA1.
(ix) INTP4 to INTP6 (interrupt request from peripherals) ... Input
These are the external interrupt request input pins.
(iix) KR6, KR7 (key return) ... Input
These are the key interrupt input pins. Their operation is specified by the key return mode register
(KRM) in the input port mode.
(8) PCM0 to PCM3 (port CM) ... I/O
Port CM is a 4-bit I/O port for which input and output can be set in 1-bit units.
In addition to functioning as an I/O port, PCM0 to PCM3 can also be used for wait insertion signal input,
internal system clock output, and bus hold control signal I/O in the control mode.
The port mode and control mode can be selected as the operation mode for each bit, and are specified by the
port CM mode control register (PMCCM).
(a) Port mode
PCM0 to PCM3 can be set to input or output in 1-bit units by the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM3 can be set to the port mode or control mode in 1-bit units by the PMCCM register.
(i) WAIT (wait) ... Input
This is a control signal input pin that inserts data waits in a bus cycle. This pin supports
asynchronous input for CLKOUT. In the multiplex mode, sampling starts at the falling edge of the
CLKOUT signal in the T2 and TW states of the bus cycle. In the separate mode, sampling starts at
the rising edge of the CLKOUT signal in the T1 and TW states of the bus cycle. If the setup/hold
times in the sampling timing are not satisfied, wait insertion may not be performed.
User’s Manual U15862EJ3V0UD
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NEC [ NEC ]
