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UPD703208GKA-XXX-9EU 参数 Datasheet PDF下载

UPD703208GKA-XXX-9EU图片预览
型号: UPD703208GKA-XXX-9EU
PDF下载: 下载PDF文件 查看货源
内容描述: 32位单芯片微控制器产品 [32-Bit Single-Chip Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 757 页 / 4297 K
品牌: NEC [ NEC ]
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CHAPTER 2 PIN FUNCTIONS  
Table 2-3. Pin Operation Status in Operation Modes of V850ES/KG1  
Operating Status  
ResetNote 1  
HALT Mode  
IDLE Mode/  
STOP Mode  
Idle StateNote 2  
Bus Hold  
Pin  
AD0 to AD15 (PDL0 to PDL15)  
A0 to A15 (P90 to P915)  
A16 to A21 (PDH0 to PDH5)  
WAIT (PCM0)  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Hi-Z  
Hi-Z  
Hi-Z  
Held  
Hi-Z  
Hi-Z  
Held  
Held  
Hi-Z  
CLKOUT (PCM1)  
L
Operating  
Operating  
Hi-Z  
CS0, CS1 (PCS0, PCS1)  
WR0, WR1 (PCT0, PCT1)  
RD (PCT4)  
H
Held  
H
H
Hi-Z  
H
H
Hi-Z  
ASTB (PCT6)  
H
H
Hi-Z  
HLDAK (PCM2)  
H
H
L
HLDRQ (PCM3)  
Operating  
Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset.  
2. The pin statuses in the idle state inserted after the T3 state in the multiplex mode and after the T2 state  
in the separate mode are listed.  
Remark Hi-Z: High impedance  
H:  
L:  
–:  
High-level output  
Low-level output  
Input without sampling (input acknowledgement not possible)  
Table 2-4. Pin Operation Status in Operation Modes of V850ES/KJ1  
Operating Status  
ResetNote 1  
HALT Mode  
IDLE Mode/  
STOP Mode  
Idle StateNote 2  
Bus Hold  
Pin  
AD0 to AD15 (PDL0 to PDL15)  
A0 to A15 (P90 to P915)  
A16 to A23 (PDH0 to PDH7)  
WAIT (PCM0)  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Operating  
Hi-Z  
Hi-Z  
Hi-Z  
Held  
Hi-Z  
Hi-Z  
Held  
Held  
Hi-Z  
CLKOUT (PCM1)  
L
Operating  
Operating  
Hi-Z  
CS0 to CS3 (PCS0 to PCS3)  
WR0, WR1 (PCT0, PCT1)  
RD (PCT4)  
H
Held  
H
H
Hi-Z  
H
H
Hi-Z  
ASTB (PCT6)  
H
H
Hi-Z  
HLDAK (PCM2)  
H
H
L
HLDRQ (PCM3)  
Operating  
Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset.  
2. The pin statuses in the idle state inserted after the T3 state in the multiplex mode and after the T2 state  
in the separate mode are listed.  
Remark Hi-Z: High impedance  
H:  
L:  
–:  
High-level output  
Low-level output  
Input without sampling (input acknowledgement not possible)  
User’s Manual U15862EJ3V0UD  
65  
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