µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Figure 7-1. DMA Function Block Diagram
Internal RAM
Internal peripheral I/O
Internal bus
Internal peripheral I/O bus
CPU
DMA source address
register (DSAnH/DSAnL)
Data control
Address control
DMA destination address
register (DDAnH/DDAnL)
DMA byte count register
(DBCn)
TCn
NMI
Count control
DMA addressing control
register (DADCn)
DMA channel control
register (DCHCn)
INTPmn
Request from on-chip
peripheral I/O
Channel control
DMA disable status
register (DDISn)
DMA restart register
(DRSTn)
DMARQn
DMAAKn
DMA trigger source
register (DTFRn)
DMAC
Bus interface
V850E/MS1
External bus
External ROM
External I/O
External RAM
Remark m = 10 to 15, n = 0 to 3
30
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
