Figure 7-1. Block Diagram of Timer 50
Internal bus
8-bit timer mode
control register 50
(TMC50)
P31
output latch
TEG50
TCE50
TCL502 TCL501 TCL500 TMD501 TMD500
TOE50
PM31
8-bit compare
register 50 (CR50)
Decoder
To Figure 7-2 (F)
Match
Timer 50 match signal
(in cascade connection mode)
Bit 7 of TM60
(from Figure 7-2 (A))
INTTM50
f
X
f
X
/23
/27
OVF
f
X
8-bit timer counter 50
(TM50)
S
R
TO50/TMI60/INTP1/P31
f
XT
IN
Q
Q
Timer 60 interrupt request signal
(from Figure 7-2 (B))
Clear
Selector
CK
Carrier clock
(in carrier generator mode)
or timer 60 output signal
(in a mode other than carrier generator mode)
(from Figure 7-2 (C))
To Figure 7-2 (G)
Timer 50 match signal
(in carrier generator mode)
Cascade connection
mode
PWM mode
From Figure 7-2 (E)
Timer 60 match signal
(in cascade connection mode)
From Figure 7-2 (D)
Count operation start signal
(in cascade connection mode)
NEC [ NEC ]
