DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down
exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.
Active Power-Down Entry and Exit timing diagram
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tc0
CK
CK
CMD
Valid
NOP
NOP
NOP
NOP
NOP
NOP
tIS
tPD
tIH
CKE
Valid
Valid
tIH
tIS
tCKE
Address
Valid
Valid
tCPDED
tXP
Enter
Power-Down
Exit
Power-Down
Do not
care
Time
Break
Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate,
Precharge, Refresh, MRS:
Power-Down Entry after Read and Read with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Ta8
Tb0
Tb1
CK
CK
RD or
RDA
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Valid
Valid
tIS
tCPDED
CKE
tPD
Address
Valid
Valid
RL = AL + CL
DQS,
DQS
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
BL8
BC4
Din
b
Din
b+1
Din
b+2
Din
b+3
tRDPDEN
Power-Down
Entry
Do not
care
Time
Break
Version 2.3
02/2017
67
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