DDR3(L) 4Gb SDRAM
NT5CB(C)512M8DN / NT5CB(C)256M16DP
READ Operation
Read Burst Operation
During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or
WRITE (AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
Read Burst Operation RL=5 (AL=0, CL=5, BL=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
CK
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank
Col n
Address
tRPRE
tRPST
DQS, DQS
DQ
Dout
n
Dout
n +1
Dout
n +2
Dout
n +3
Dout
n +4
Dout
n +5
Dout
n +6
Dout
n +7
CL=5
RL = AL + CL
Notes:
1. BL8, RL = 5, AL = 0, CL = 5.
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK
CK
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank
Col n
Address
AL = 4
tRPRE
DQS, DQS
DQ
CL=5
Dout
n
Dout
n +1
Dout
n +2
RL = AL + CL
Notes:
1. BL8, RL = 9, AL = (CL - 1), CL = 5.
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
Version 2.3
02/2017
50
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