NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
MPR MR3 Register Definition
Read Address
Burst Order
MR3 A[2]
MR3 A[1:0]
Function
Burst Length
A[2:0]
and Data Pattern
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern
[0,1,0,1,0,1,0,1]
BL8
000b
Read Predefined
Pattern for System
Calibration
Burst order 0,1,2,3
1b
00b
BC4
BC4
000b
100b
Pre-defined Data Pattern [0,1,0,1]
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
BL8
BC4
BC4
BL8
000b
000b
100b
000b
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
1b
1b
1b
01b
10b
11b
RFU
RFU
RFU
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
BL8
BC4
BC4
100b
000b
000b
100b
Burst order 4,5,6,7
Burst order 0,1,2,3,4,5,6,7
Burst order 0,1,2,3
Burst order 4,5,6,7
NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
Version 1.4
05/2019
27
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