NTC Proprietary
Level: Property
DDR3(L)-2Gb SDRAM
NT5CB(C)256M8JQ/NT5CB(C)128M16JR
Address / Command Setup, Hold, and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)
and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew
rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal from the ac
level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the
first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between
shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew
rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal from the dc
level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac)
for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have
reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL(ac).
ADD/CMD Setup and Hold Base-Values for 1V/ns
Grade
Symbol
Reference
VIH/L(ac)
VIH/L(ac)
VIH/L(ac)
VIH/L(ac)
VIH/L(dc)
VIH/L(ac)
VIH/L(ac)
VIH/L(ac)
VIH/L(ac)
1600
1866
-
2133
Unit
ps
Notes
tIS(base) AC175
tIS(base) AC150
tIS(base) AC135
tIS(base) AC125
tIH(base) DC100
tIS(base) AC160
tIS(base) AC135
tIS(base) AC125
tIH(base) DC90
45
-
1
1
170
-
-
-
60
135
95
-
ps
DDR3
65
ps
1
-
150
100
-
ps
1
120
60
ps
1
ps
1
185
-
65
-
ps
1,2
1,3
1
DDR3L
150
110
-
ps
130
-
ps
NOTE 1 (AC/DC referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK- slew rate)
NOTE 2 The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for DDR3L-
800/1066 or 100 ps for DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account
for the earlier reference point [(160 mV - 135 mV) / 1 V/ns].
NOTE 3 The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866
of derating to accommodate for the lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point [(135 mV -
125 mV) / 1 V/ns].
Version 1.4
05/2019
142
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