NT5DS4M32EG
NanoAmp Solutions, Inc.
Advance Information
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs /CAS
latency, address mode, burst length, test mode, DLL reset and various vendor specific option to make DDR SDRAM
useful for variety of different applications. The default value of the mode register is not defined, therefore the mode
register must be written after EMRS setting for proper operation. The mode register is written by asserting low on /CS,
/RAS, /CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode
register). The state of address pins A0 ~ A11 and BA0,BA1 in the same cycle as /CS, /RAS, /CAS and /WE going low
is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode
register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on
functionality. The burst length uses A0~A2, address mode uses A3, /CAS latency (read latency from column address)
uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL for DLL reset. A7, A8, BA0, and BA1 must be set to low for
normal MRS operation. Refer to the table for specific codes for various burst length, address modes and /CAS
latencies.
Address Bus
BA1
RFU
BA0
0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode
Register
RFU
DLL
TM
/CAS Latency
BT
Burst Length
Burst Type
A3
Type
DLL
Test Mode
0
1
Sequential
Interleave
A8
0
DLL Reset
No
A7
0
Mode
Normal
Test
1
Yes
1
Burst Length
/CAS Latency
Burst Type
A2
A1
A0
BA0
0
Mode
A6
0
A5
0
A4
0
Latency
Sequential
Interleave
Reserved
2
MRS
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
1
EMRS
0
0
1
Reserved
2
0
1
0
4
4
0
1
1
3
8
8
Reserved
Reserved
1
0
0
Reserved
Reserved
Reserved
Full page
Reserved
Reserved
Reserved
Reserved
* RFU(Reserved for future use)
should stay “0” during MRS cycle.
1
0
1
1
1
0
Reserved
Reserved
1
1
1
Figure 5: MRS Cycle
1
2
3
4
5
6
7
8
0
/CK
CK
Precharge
All Banks
Any
Command
1
Command
NOP
NOP
NOP
MRS *
NOP
NOP
NOP
tRP * 2
tMR D = 2 tCK
* 1 : MRS can be issued only at all banks precharge state.
* 2 : Minium tRP is required to issue MRS command.
Doc # 14-02-045 Rev A ECN 01-1118
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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NANOAMP [ NANOAMP SOLUTIONS, INC. ]
