NT5DS4M32EG-6 参数 Datasheet PDF下载

NanoAmp Solutions, Inc.

NT5DS4M32EG

Advance Information

Figure 2: FUNCTIONAL BLOCK DIAGRAM (1Mbit x 32 I/O x 4 Bank)

32

Input Buffer

LWE

I/O Control

CK, /CK

Bank Select

Data Input Register

Serial to parallel

64

LDMi

1M x 32

2-bit prefetch

Output Buffer

Sense AMP

Refresh Counter

Row Buffer

1M x 32

1M x 32

1M x 32

Row Decoder

64

32

x32

DQi

CK,/CK

Address Register

ADDR

Column Decoder

LRAS

LCBR

Column Buffer

Latency & Burst Length

•

Strobe

Gen.

LCKE

LRAS

LCBR

LWE

Programming Register

DLL

LCAS

LWCBR

LDMi

CK,/CK

Timing Register

CK,/CK

CKE

/CS

/RAS

/CAS

/WE

DMi

Doc # 14-02-045 Rev A ECN 01-1118

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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