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See Timing Diagrams: Timing Data for Result Port
Interface and Table 1 for the Result Port bit descriptions.
Note:
Although the result data register also can be read through
the processor port, it is important to note that the means of
retrieving the data must be unique. Therefore, if the user is not
using the Result Port Interface, but is reading result data through
the processor port, RP_NXT and RP_SEL should be pulled low.
This ensures that all result data remains in the Result Data
register until read through the processor port. RP_NXT and
RP_SEL should be pulled low to 0 volts through a pull-down
resistor (typically 10k ohms).
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See Timing Diagrams: Timing Data for Control Interfaces.
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SYSCLK is the user-supplied system clock for
synchronous chip operation. Optimum results are achieved
when the SYSCLK is 50 MHz, although it may run slower
with fewer than 8 ports and with an increased allowance
for latency. The duty cycle must be between 45 to 55
percent.
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When system Reset is taken LOW, all internal
state-machines are reset to their initial state and any data is
cleared. All registers are returned to default values.
/RESET is synchronous and should be held LOW for a
minimum of two SYSCLK cycles. The user must set the
LANCAM Segment Control register after asserting
/RESET.
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INCR is a user command to invoke the built-in purge
routine. Both STCURR and STPURG 8-bit counters are
advanced one count on the rising edge of INCR, and the
time stamp stored with each LANCAM entry is compared
with STPURG. Matching entries subsequently are purged
or deleted. This pin must be configured, if it is required, by
setting bit 2 and bit 3 in the System Target (STARG)
register. Each counter can be incremented individually
through the Processor Port. (see Operational
Characteristics: STARG System Target Register
Mapping).
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The Result Port Data carries the results of recently
processed packets detected on the MII ports. See Table 1
for details of the Result Port Data bit descriptions. These
are identical to the Result Data register bits.
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The Result Port Data Valid indicates that the RP port
carries valid packet data. As long as there is valid packet
data, RP_DV will stay HIGH.
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The Result Port Next pin brings the next result to the RP
bus if RP_SEL is asserted. If there are no additional results
available, the RP_DV will drop LOW after the time
interval specified in the Result Port Timing specification.
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The Result Port Select pin controls RP[15:0] and
RP_NXT. RP_NXT and RP_SEL are connected by a
logical AND. Therefore, RP_SEL must be HIGH in order
for RP_NXT to bring the next result to the RP bus. RP and
RP_NXT from two MU9C8358L components (eight
ports) can be wired together on a common bus in order to
run these components in cascade. Refer to Figure 7 on
MU9C8358L is being implemented. As long as there is
valid packet data, RP_DV will stay HIGH.
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