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The system should decode one unique range of addresses
to produce an individual chip select (/PCS) signal for each
MU9C8358L component. The lowest address in this
application-defined address range is referred to as
CHIP_BASE. One set of these registers is available for
each MU9C8358L in a system. Table 20 shows the Chip
registers and their address values.
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The Result Status register is used to convey whether the
Result Data register stores any valid result data. Reading
this register resets the /INTR pin if it was asserted because
of result data being processed (after all valid result data is
read).
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The Chip Role register stores the designation of each
MU9C8358L. When two MU9C8358Ls are chained
together the device that is hardware configured as the
MASTER device must have this register loaded with
000H. The other MU9C8358L must be designated as the
SLAVE and be loaded with any other value other than
000H. When only one MU9C8358L is used it must be
designated as MASTER.
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The Result Data register stores the result of the automatic
SA and DA processing.
Note: Any access to the System registers using /PCSS are ignored
until this register is properly set. This occurs because the
CHIPROL register always defaults to a SLAVE designation.
Therefore, the system software MUST configure the CHIPROL
register(s) before any System register accesses are made.
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The Chip Version register stores the version of the chip.
The value of this read-only register will be incremented
for each subsequent release.
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MUSIC [ MUSIC SEMICONDUCTORS ]
