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When the host CPU wishes to write to the LANCAM (at
initialization) bit 4 is set to one while setting bits 3–0 to
the values required for a LANCAM data or command
cycle. The data or command to be transferred to the
LANCAM should be loaded into the SCDW0 register
prior to the cycle being initiated. Each LANCAM cycle is
a four step process and is described as follows:
This register establishes the number of clock cycles that
DA and SA operations will take. This is based on the
speed of the attached LANCAM components.
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1. Load SCDW0 with 16-bit data or command.
2. Load SLCCS with cycle value to take /E HIGH.
3. Load SLCCS with cycle value to take /E LOW.
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4. Load SLCCS with cycle value to take /E HIGH. For
example a TCO CT command cycle would be SCDW0
= 0200H, SLCCS = 19H, 11H, 19H.
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The Status Word registers store the 32-bit LANCAM
status register value after the LANCAM entry read routine
is performed.
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SCSWA stores the lower 16 bits of the status register
SCSWB stores the upper 16 bits.
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The SA Op-Code registers store the LANCAM Op-Code
values required when the MU9C8358L performs the
automatic SA search routine.
The System Command registers allow the CPU to execute
transactions applied to a LANCAM array. There are seven
command registers and they have the prefix SDO. Each
register is used to initiate a built-in routine that allows
general LANCAM housekeeping tasks to be performed.
The housekeeping sequence is initiated by writing any
arbitrary value to the appropriate register.
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SSAU stores the code required to update an SA
SSAL stores the code required to learn an SA.
These registers have the default values required to perform
the routines described in Built-in Routines.
Descriptions of the routines performed when SDO_ADD,
SDO_DELETE, SDO_READ, and SDO_SETADD are
accessed as shown in Built-in Routines. SDO_INCTS,
SDO_INCPR, and SDO_INCTSPR control the time stamp
counters. SDO_INCPR and SDO_INCTSPR also cause
the purge routine described in Built-in Routines to be
initiated. The MU9C8358L may hold PROC_RDY
inactive if it is processing any high-priority DA and SA
searches. The registers and their address values are found
in Table 3.
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The System LANCAM Control register enables the host
CPU to initialize and configure the LANCAMs. During
normal system operation bit 4 should be set to zero to
disable the LANCAM control bits.
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MUSIC [ MUSIC SEMICONDUCTORS ]
