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The System Dynamic Configuration Register (SDCFG)
allows the CPU to control the MU9C8358L /RESET_LC
output pin. This pin normally would be connected to the
/RESET input of all the LANCAMs in a chain of
LANCAMs. When the RST_CAM bit is logic 0 the
/RESET_LC output is LOW and when the RST_CAM bit
is logic 1 the /RESET_LC output is HIGH. Note that if a
hardware reset is performed by taking the MU9C8358L
/RESET input LOW, /RESET_LC is asserted LOW.
However, once /RESET has been taken HIGH,
/RESET_LC remains LOW, holding the LANCAM(s) in
the reset condition. The RST_CAM bit must be set to 1 to
return /RESET_LC HIGH and hence allow the
LANCAMs to operate normally.
When using the series of built-in routines, the SCDW
registers are used to transfer data. The bit mapping is
different for each routine. Please refer to the appropriate
mapping for the relevant routine. Also refer to the MAC
Address Storage section on page 11.
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During the LANCAM initialization and configuration
process, SCDW0 is used with SLCCS to configure the
LANCAMs. When SCDW0 is used to transfer associated
data, the bit mapping is as shown.
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The System Target Register (STARG) allows the CPU to
determine how events are to be handled. The INCR_PIN
bits enable or disable to INCR hardware input. The
EN_FF_INT bits enable or disable whether the LANCAM
/FF output produces an interrupt when the LANCAM is
full.
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The System Time Stamp Purge register (STPURG) stores
the purge time stamp value. It is a read-only register, but it
may be incremented by writing an arbitrary value to the
SDO_INCPR register.
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The System Time Stamp Current register (STCURR)
stores the current time stamp value. It is a read-only
register, but it may be incremented by writing an arbitrary
value to the SDO_INCTS register.
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