Functional Description
MU9C8338A 10/100Mb Ethernet Filter Interface
MAC Address Storage
When the MU9C8338A performs an SA processing
function, it automatically extracts the MAC address from
the packet. The database is searched and the MAC address
is added to the LANCAM database if necessary. Similarly,
when a DA processing function is performed, the
MU9C8338A automatically searches the database for the
extracted DA MAC address.
It is important that the user is aware of the byte ordering of
the 48-bit MAC address when it is stored in the LANCAM
database. This is because the user must byte-order MAC
addresses identically when a database entry is to be
manually added or deleted. Similarly, if the user wishes to
read out a MAC address, they should also be aware of the
byte ordering when the relevant data registers are read.
Throughout this data sheet MAC addresses are shown as
bit 47 being the most significant bit, which is placed on the
left. Similarly, bit 0 is shown as the least significant bit and
placed on the right. Using this notation, the
Individual/Group (I/G) bit subfield would be shown as bit
40. This bit would be the first bit of an address transmitted
onto the serial network and also the first bit received. The
IEEE 802.3 refers to the I/G bit subfield as bit 0. If the bit
is set to 1, it indicates that the address is a group address.
Conversely, if the bit is set to 0, it indicates it is an
individual address. Figure 4 shows a typical 48-bit MAC
address used in Ethernet or IEEE 802.3 networks.
MAC Address
47
02
40
:
39
60
32
:
31
8C
24
:
23
12
16 15
:
34
08
:
07
56
00
If the user wishes to use the built-in routines to manually
add, delete, or read MAC addresses from the database, the
System CAM Word registers (SCDW) are used as shown
in Figure 5. It shows how the MAC address, used as an
example in Figure 4, would be transferred using the
SCDW registers.
If the user intended to delete the MAC address, the SCDW
registers would be written as shown in item 1 and the
SDO_DELETE routine would be invoked.
If the user intended to add the address manually, the
SCDW registers would be written as shown in item 2 and
the SDO_ADD routine would be invoked.
Finally, if the user intended to read an entry, the
SDO_READ routine would be invoked and the address
would be read from the SCDW registers as shown in item
3. The built-in routines are explained more fully later in
this document.
1
SCDW3
SDO_DELETE
not used
SCDW2
6002
SCDW1
128C
SCDW0
5634
2
SCDW3
SDO_ADD
6002
SCDW2
128C
SCDW1
5634
SCDW0
assoc. data
3
SCDW3
SDO_READ
6002
SCDW2
128C
SCDW1
5634
SCDW0
assoc. data
Figure 5: SCDW Register Order
Functional Blocks
The building blocks that make up the MU9C8338A are
shown in Figure 3, and their functions are described by the
following.
MII Interface (MII Port)
0000 0010
IEEE bit 0
I/G bit
LANCAM Database Entry
seg 3
6002
seg 2
128C
seg 1
5634
seg 0
assoc. data
The incoming asynchronous receive data is registered for
subsequent processing. MU9C8338A internal processing
is synchronous with the system clock.
Tag Port Interface (Tag Port)
Figure 4: MAC Address Byte Order
If the MAC address shown in Figure 4 is added to the
database by the MU9C8338A, it is stored as follows:
•
•
•
•
Segment 3 = 6002h
Segment 2 = 128Ch
Segment 1 = 5634h
Segment 0 = Associated data (permanent bit, time
stamp and port ID)
Rejection of a packet is indicated by the assertion of REJ.
The FRX_ER line, which otherwise reflects the state of
the RX_ER pin, is forced to HIGH at the same time. If the
DA is matched in the LANCAM, the TP_DV pin is
asserted and the destination port ID, high-order bit first, is
clocked out through the TP_SD pin transitioning after the
RX_CLK rising edge.
MAC Receiver
This block performs tasks that are a subset of the Ethernet
MAC. It detects errors, (CRS, COL, RX_ER, and Runt
Frame), determines the start of frame, parses addresses,
computes the CRC for 10Base-X packets, and formats the
4-bit nibbles into 48-bit SA and DA registers.
9
Rev. 0a
MUSIC [ MUSIC SEMICONDUCTORS ]
