Functional Description
MU9C8338A 10/100Mb Ethernet Filter Interface
FUNCTIONAL DESCRIPTION
Internal Functions
MU9C8338A internal functions are shown in Figure 3.
Before discussing the individual blocks, the underlying
principles are presented. The network interface is
monitored for network and data symbol errors. Receive
data [RXD] is clocked into a register using the 25MHz
recovered clock for 100Base-X or 2.5MHz clock for
10Base-X. The Preamble and Start Frame delimiter (SFD)
are scanned to locate the Destination address (DA) and the
Source address (SA).
The LANCTL block generates the command cycles and
operational codes to complete CPU-requested actions and
network-generated requests. The CPU must initialize the
CAM, write the permanent station list, and initiate other
housekeeping functions. Network traffic initiates DA
filtering, SA learning, and time stamp updates. All
state-machines required for real-time operations are
implemented in the ASIC hardware; the host CPU runs the
non-time-critical initialization routine.
The MU9C8338A schedules communication with the host
processor and the CAM through an arbitration process.
Once the system is initialized and configured,
highest-priority is given to network traffic.
Information on the LANCAM operation and instruction
set can be found in the appropriate LANCAM data sheet
for each device.
LANCAM Bus
FRX_ER
REJ
Tag Port
Interface
TP_SD
LANCAM
Interface
TP_DV
RX_DV
RX_ER
RXD[3:0]
MII
Interface
RX_CLK
MAC
Receiver
CRS
COL
TCK
LANCTL
TMS
TDI
JTAG
Controller
Configuration,
Control and Status
Registers
Host CPU
Interface
CPU Bus
TDO
/TRST
Result Bus
Interface
Result Bus
FIFO
Figure 3: Functional Block Diagram
Rev. 0a
7
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