MU9C8148
SWITCHING CHARACTERISTICS (CONT’D)
Host Processor Interface Switching Characteristics
Intel Mode Timing
No. Symbol
Parameter
Min
Max
Units Notes
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
tSHSL
/CS HIGH Pulse Width
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSLKL
/CS LOW to ALE LOW Setup Time
ALE HIGH Pulse Width
2
tKHKL
2
tAVKL
Address Bus Valid to ALE LOW Setup Time
Address Bus Invalid from ALE LOW Hold Time
ALE LOW to /WS or /RS LOW Setup Time
/WS LOW to /HBDIR LOW Delay Time
/WS LOW to /HBEN LOW Delay Time
/HBDIR LOW to /HBEN LOW Delay Time
/WS LOW to Data Input Valid Delay Time
/WS LOW to /HBRDY LOW Delay Time
/HBRDY LOW to Data Input Invalid Hold Time
/HBRDY LOW to /WS or /RS HIGH Setup Time
2
tKLAX
5
tKLWRL
tWLBDL
tWLBEL
tBDLBEL
tWLDV
tWLRDL
tRDLDX
tRDLWRH
0
tCLCL + 3
tCLCL + 3
10
3 •tCLCL
3 • tCLCL + 3
tCLCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2
0
tRWHWRL /WS or /RS HIGH Pulse Width
2 • tCLCL
tCLCL + 3
tCLCL + 3
3
tWHBDH
tWHBEH
/WS HIGH to /HBDIR HIGH Delay Time
/WS HIGH to /HBEN HIGH Delay Time
2 • tCLCL + 20
2 • tCLCL + 20
tCLCL + 20
tRWHRDH /WS or /RS HIGH to /HBRDY HIGH Delay Time
tRWHRDZ
tSHRDZ
tRLBEL
tRLRDL
tDVRDL
tRHBEH
tRHDZ
/WS or /RS HIGH to /HBRDY Hi-Z Delay Time
/CS HIGH to /HBRDY Hi-Z Delay Time
/RS LOW to /HBEN LOW Delay Time
tCLCL + 3
tCLCL + 3
2 • tCLCL + 3
3 • tCLCL + 3
2
2 • tCLCL + 20
tCLCL + 20
1
/RS LOW to /HBRDY LOW Delay Time
Data Output Valid to /HBRDY LOW Setup Time
/RS HIGH to /HBEN HIGH Delay Time
/RS HIGH to Data Output Hi-Z Delay Time
1, 3
tCLCL + 3
tCLCL + 3
2 • tCLCL + 20
2 • tCLCL + 20
Motorola Mode Timing
No. Symbol
Parameter
Min
Max
Units Notes
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
tSHSL
/CS HIGH Pulse Width
0
ns
ns
ns
ns
ns
tSLDSL
/CS LOW to /UDS or /LDS LOW Setup Time
SRNW Valid to /UDS or /LDS LOW Setup Time
Address Bus Valid to /UDS or /LDS LOW Setup
/UDS or /LDS LOW to /HBDIR LOW Delay Time
/UDS or /LDS LOW to /HBEN LOW Delay Time
/HBDIR LOW to HBEN LOW Delay Time
/UDS or /LDS LOW to Data Input Valid Delay
/UDS or /LDS LOW to /HBRDY LOW Delay Time
/HBRDY LOW to Data Input Invalid Hold Time
/HBRDY LOW to /UDS or /LDS HIGH Setup Time
/UDS or /LDS HIGH Pulse Width
0
tSRVDSL
tAVDSL
2
2
tDSLBDV
tDSLBEL
tBDLBEL
tDSLDV
tDSLRDL
tRDLDX
tRDLDSH
tDSHDSL
tDSHSRX
tDSHAX
tDSHBDX
tCLCL + 3
R • tCLCL + 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 4
1, 5
10
3 •tCLCL
3 • tCLCL + 3
tCLCL
0
2 • tCLCL
0
/UDS or /LDS HIGH to SRNW Invalid Hold Time
/UDS or /LDS HIGH to Address Bus Invalid Hold
/UDS or /LDS HIGH to /HBDIR Invalid Delay
10
tCLCL + 3
2 • tCLCL + 20
Rev. 5.5 Draft web
18
MUSIC [ MUSIC SEMICONDUCTORS ]
