MU9C8148
Motorola Mode Timing (con't)
Min
No. Symbol
Parameter
Max
Units Notes
52
53
54
55
56
57
tDSHBEH
tDSHRDH
tDSHRDZ
tSHRDZ
tDVRDL
/UDS or /LDS HIGH to /HBEN HIGH Delay
/UDS or /LDS HIGH to /HBRDY HIGH Delay Time
/UDS or /LDS HIGH to /HBRDY Hi-Z Delay Time
/CS HIGH to /HBRDY Hi-Z Delay Time
tCLCL + 3
3
2 • tCLCL + 20
tCLCL + 20
ns
ns
ns
ns
ns
ns
tCLCL + 3
tCLCL + 3
2
2 • tCLCL + 20
tCLCL + 20
Data Output Valid to /HBRDY LOW Setup Time
/UDS or /LDS HIGH to Data Output Hi-Z Delay
tDSHDZ
tCLCL + 3
2 • tCLCL + 20
LANCAM Interface Switching Characteristics
No. Symbol Parameter
Min
Typ.
Max
Units
ns
Notes
58
59
60
61
62
63
tELEH
/E LOW Period
4 • tCLCL
R • tCLCL
tEHEL
/E HIGH Period
ns
7
tCDVEL
tELCDX
tDVEH
tEHDX
Control/Data Setup Time to /E LOW
Control/Data Hold Time from /E LOW
Data Setup Time to /E HIGH
Data Hold Time to /E HIGH
1
120
tCLCL
0
ns
ns
ns
ns
Notes
1. If there are routines running due to network activity, access to the device is arbitrated and these times will be
extended by an integer number of RXC cycles, the duration of which will be indicated by /INT going LOW.
2. For non-arbitrated accesses, tWLRDL is 3 RXC cycles for Register writes and for the first write to the
Instruction Buffer, 6 RXC cycles for the second write to the Instruction Buffer or the FIFO, and 9 RXC cyles
for LANCAM writes.
3. For non-arbitrated accesses, tRLRDL is 3 RXC cycles for Register reads, 6 RXC cycles for Instruction Buffer
and FIFO reads, and 9 RXC cycles for LANCAM reads.
4. For non-arbitrated accesses, “R” is 1 for Write cycles and 2 for Read cycles.
5. For non-arbitrated accesses, tDSLRDL is 3 RXC cycles for Register and Instruction Buffer writes, 9 RXC
cycles for LANCAM writes, 3 RXC cycles for Register reads, 6 RXC cycles for Instruction Buffer reads, and 9
RXC cycles for CAM reads.
6. Although the host interface is asynchronous, RXC is used internally to control operations. Therefore, for
modeling purposes, /WS, /RS, /UDS and /LDS can be assumed to have a 10ns setup time with respect to the
rising edge of RXC and /INT, /HBRDY and /FULL can be assumed to assert within 20ns of the rising edge of
RXC. XMATCH and XFAIL assert four RXC cycles after the /MI input is valid.
7. For a data move from DQ15-DQ0 to address, R is 3. For a data move from address to DQ15-DQ0, R is 4.
For a LANCAM register write then read, R is 8. For a LANCAM register write then write, or read then read, R
is 9. For a LANCAM register access read then write, R is 10.
TIMING DIAGRAMS
RXC
/RQ (SLAVE)
1
1
2
/RQI (SLAVE)
3
MU9C8148 ARBITRATION TIMING
Rev. 5.5 Draft web
19
MUSIC [ MUSIC SEMICONDUCTORS ]
