MU9C8148
REGISTER SET DESCRIPTION (CONT’D)
BIT
NAME
DESCRIPTION
11H: Start Address Register III
15 Reserved
14–8 STARTV6–0
STARTV6–0 contain the start address of Routine 5.
7
Reserved
6–0
STARTIV6–0
STARTIV6–0 contain the start address of Routine 4.
12H: Start Address Register IV
15–7 Reserved
6–0
STARTVI6–0
STARTVI6–0 contain the start address of Routine 6.
13H: FIFO Control Register
15–11 Reserved
10
ENBLFIFO
RESETFIFO
F/E
ENBLFIFO enables/disables the FIFO function in the IB. If this ENBLFIFO is HIGH, the FIFO function is
active. If ENBLFIFO is LOW the FIFO function is inactive and the /FULL, /EMPTY signal is set HIGH.
If RESETFIFO is made HIGH, the FIFO read and write pointer are reset to location 7FH. All data stored
in the FIFO is lost after a reset.
If F/E is made HIGH the /FULL, /EMPTY output functions like a FIFO full flag. At the moment the FIFO is
filled, the /FULL signal is made LOW. If F/E is LOW, the /FULL, /EMPTY output acts like a FIFO empty
flag. It goes LOW when the FIFO is empty.
9
8
7
6–0
Reserved
LIM6–0
LIM6–0 contain the lowest location in the IB the FIFO can use. The FIFO is located between LIM6–0 and
7FH.
14H: FIFO Register
15–0 FF15–0
FF15–0 contain data that is written in, or read from the FIFO. This data is stored or read from in the
location pointed to by the FIFO pointer. If the /FULL flag indicates that the FIFO is full, the data is lost. If
the /EMPTY flag indicates that the FIFO is empty, no valid data is read.
15H: Frame Counter
15–0 FC15–0
The frame counter bits FC15–0 contain the number of frames counted on the Token RIng. It is a 16-bit
counter which is increased every time a frame (SD and Token bit set to ONE) is received on the
Transceiver Interface. After overflow, this counter restarts at 0000H.
16H: Data Counter
First Access
15–0 DC31–16
DC31–16 contain the most significant part of the count of data bytes after the SA received on the
Transceiver interface. It stops counting after the ED is received, or an SD in an error situation. If there
are other Host Processor cycles between the two consecutive accesses, the result of the second read
out will repeat most significant part of the counter. After overflow, this 32-bit counter starts over at zero.
Second Access
15–0 DC15–0
DC15–0 contain the least significant part of the count of data bytes received from the Token RIng.
17H: Error Counter
First Access
15–8 DUPL7–0
DUPL7–0 contain the value of the DUPLOUT counter, which totals the number of frames that were
discarded due to a duplicate LOUT on SRF frames. After readout this error counter is reset to 00H.
IRI7–0 contain the value of the INVALIDRI counter, which totals the number of frames discarded due to
various format errors. After readout this error counter is reset to 00H.
7–0
IRI7–0
Rev. 5.5 Draft web
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MUSIC [ MUSIC SEMICONDUCTORS ]
