MU9C8148
REGISTER SET DESCRIPTION (CONT’D)
BIT
NAME
DESCRIPTION
1
2TRENBL
If 2TRENBL is LOW, every reserved type 2 frame not containing an RIF is discarded. The MAC is
signalled to flush the frame. If 2TRENBL is HIGH, the 2TRFILT bit determines if the frame is filtered or
copied directly. If TBO is HIGH, filtering is also done on reserved type 2 frames with an RIF.
If 2TRFILT is LOW, the MU9C8148 signals the MAC chip to copy every reserved type 2 frame not
containing an RIF. If 2TRFILT is HIGH, the MU9C8148 checks the DA and forwards the frame if the
forwarding conditions are met, whether or not the frame contains an RIF.
0
2TRFILT
02H: Transparent Bridging Register
15
14
PONNE
DISGA
If PONNE is LOW, the MU9C8148 performs negative filtering (Routine 0) for frames without an RIF, or
for all frames when TBO is HIGH. If PONNE is HIGH positive filtering is performed.
If DISGA is HIGH, all frames with a DA containing a group address and not containing an RIF (or all
frames with a DA containing a group address when TBO = HIGH) are discarded if PONNE is LOW. If
PONNE is HIGH, this bit becomes “don't care”.
13
12
11
10
9
DISBA
DISFA
MLRN
LLRN
If DISBA is HIGH, all frames with a DA containing a broadcast address and not containing an RIF (or all
frames with a DA containing a broadcast address when TBO = HIGH) are discarded when PONNE is
also programmed LOW. If PONNE is set HIGH, this bit becomes “don't care”.
If DISFA is HIGH, all frames with a DA containing a functional address and not containing an RIF (or all
frames with a DA containing a functional address when TBO = HIGH) are discarded when PONNE is
made LOW. If PONNE is HIGH, this bit becomes “don't care”.
If MLRN is LOW, no learning of addresses from MAC frames takes place. If this bit is set HIGH, learning
of addresses from MAC frames take place by starting Routine 1 (if starting is enabled), when the frame
doesn't contain an RIF (or for all MAC frames when TBO = HIGH).
If LLRN is LOW, no learning of addresses from LLC frames takes place. If this bit is set HIGH, learning of
addresses from LLC frames take place by starting Routine 1 (if starting is enabled), when the frame
doesn't contain an RIF (or for all LLC frames when TBO = HIGH).
If 1LRN is LOW, no learning of addresses from reserved type 1 frames takes place. If this bit is HIGH,
learning of addresses from reserved type 1 frames take place by starting Routine 1 (if starting is
enabled), when the frame doesn't contain an RIF (or for all reserved type1 frames when TBO = HIGH).
If 2LRN is LOW, no learning of addresses from reserved type 2 frames takes place. If 2LRN is set HIGH,
learning of addresses from reserved type 2 frames takes place by starting Routine 1 (if starting is
enabled), when the frame doesn't contain an RIF (or for all reserved type 2 frames when TBO = HIGH).
If MROUT is LOW, the Branch Routine Address 0 defined in the BR0START6–0 bits in IB Start Register
I is selected when a MAC frame is received. If MROUT is HIGH, Branch Routine Address 1 defined in
BR1START6–0 is selected.
If LROUT is LOW, the Branch Routine Address 0 defined in the BR0START6–0 bits in IB Start Register I
is selected when a LLC frame is received. If LROUT is HIGH, Branch Routine Address 1 defined in
BR1START6–0 is selected.
When 1ROUT is made LOW, the Branch Routine Address 0 defined in the BR0START6–0 bits in IB
Start Register I is selected when a reserved type 1 frame is received. If 1ROUT is made HIGH, Branch
Routine Address 1 defined in BR1START6–0 is selected.
1LRN
8
2LRN
7
MROUT
LROUT
1ROUT
2ROUT
6
5
4
If 2ROUT is LOW, the Branch Routine Address 0 defined in the BR0START6–0 bits in IB Start Register I
is selected when a reserved type 2 frame is received. If 2ROUT is HIGH, Branch Routine Address 1
defined in BR1START6–0 is selected.
3
2
1
0
0ENBL
1ENBL
2ENBL
Reserved
If 0ENBL is LOW, Routine 0 is disabled. If 0ENBL is HIGH, Routine 0 can be started.
If 1ENBL is set LOW, Routine 1 is disabled. If 1ENBL is HIGH, Routine 1 can be started.
If 2ENBL is LOW, Routine 2 is disabled. If 2ENBL is HIGH, Routine 2 can be started.
03H: RIF Length Register
15 Reserved
14–11 SRFRD3–0
Bits SRFRD3–0 contain the maximum number of RDs–1 for an SRF frame. SRF frames containing more
RDs are not copied by the MU9C8148.
10
Reserved
9–6
ARERD3–0
Bits ARERD3–0 contain the maximum number of RDs–1 for an ARE frame. ARE frames containing more
RDs are rejected.
5
Reserved
4–1
STERD3–0
Bits STERD3–0 contain the maximum number of RDs–1 an STE frame can contain. If an STE frame
contains more RDs, it is rejected.
0
Zero
Must be set to “0" or LOW.
Rev. 5.5 Draft web
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MUSIC [ MUSIC SEMICONDUCTORS ]
