MU9C8148
FUNCTIONAL DESCRIPTION (CONT’D)
For a non-arbitrated Write cycle, /HBEN and /HBDIR go LOW encoded data received from the Token Ring transceiver is input
after the second rising edge of RXC past the falling edge of to the RXD pin which clocked by the RXC clock. The /RDY
/WS (Intel mode) or /UDS and /LDS (Motorola mode). /HBRDY signal indicates the presence of received data on the RXD pin.
goes LOW after the second rising edge of RXC past the falling The Transceiver interface notifies the TB block and the SRB
edge of /HBEN for Register and Instruction Buffer write cycles, that it has detected a JK Start delimiter in the incoming data
and after the 8th rising edge of RXC past the falling edge of stream and to begin parsing the other fields of the frame. The
/HBEN for CAM write cycles. The write data on the D(15-0) bus Transceiver interface performs
a number of error checks:
is strobed by the rising edge of RXC that outputs /HBRDY.
whether the data contained any control characters before an
ED was received; that no second SD is received before an ED
For a non-arbitrated Read cycle, /HBEN goes LOW after the is received; and, /RDY is still asserted. In any of these cases,
third rising edge of RXC past the falling edge of /RS (Intel both the TB and SRB are notified and reception of data is
mode) or /UDS and /LDS (Motorola mode). /HBRDY goes LOW cancelled. Also checked are: the correctness of the FCS, the
after the first rising edge of RXC past the falling edge of /HBEN value of the E bit in the ED, and the values of both C bits and
for a Register read cycle, the 4th rising edge of RXC past the both A bits in the FS field. If there is an error situation detected
falling edge of /HBEN for an Instruction Buffer read cycle, and in one of these items, the TB is notified not to start Routine 1.
the 7th rising edge of RXC past the falling edge of /HBEN for a
CAM read cycle. Read data is output to the D(15-0) bus
immediately prior to /HBRDY going LOW.
Host Processor Interface
The Host Processor interface is configured for Intel or Motorola
addressing modes using the /INTEL pin. In both modes the
MU9C8148 is a slave on the processor bus and can be
programmed using the registers described in this document.
The MU9C8148 provides /HBEN and /HBDIR to enable the
user to add external bi-directional buffers in the D15-D0
datalines. In Intel mode, ALE is used to latch the address lines.
In Motorola mode, both /UDS and /LDS are used to load the
upper and lower bytes to all of the registers including the
Instruction buffer and FIFO.
For both non-arbitrated Write and Read cycles, /HBRDY goes
HIGH after the first rising edge of RXC past the rising edge of
/WS or /RS in Intel mode or /UDS, /LDS in Motorola mode.
/HBEN and /HBDIR return HIGH and /HBRDY will go
three-state after the next rising edge of RXC.
On a FIFO write, /HBRDY goes LOW after the fifth rising edge
of RXC past the falling edge of /HBEN. On a FIFO read,
/HBRDY goes LOW after the fourth rising edge of RXC past the
falling edge of /HBEN.
Two MU9C8148s Sharing One LANCAM
MAC Interface
Two MU9C8148s may share the same LANCAM string if they
The TB block and/or the SRB notify the MAC interface to copy are operating at the same frequency, using /RQ and /RQI to
or reject a frame through the XMATCH and the XFAIL pins for arbitrate the LANCAM access by setting the ASSRQ bit in the
the TMS380CX6, or the /FLUSH pin for the 82C581, using the Control register to HIGH. One MU9C8148 is set to be Master,
TEXAS bit in the Control register to select the operating mode. and given Routines 0–2, and the other is set to be Slave and
When Routine 2 is enabled, the results from the TB and the given the non-time-critical Routines 3–6 in addition to Routines
SRB are combined.
0–2. Routines 3–6 running on the Slave can be interrupted
immediately by time-critical routines running on either the
Master or Slave, but if both MU9C8148s try to run a high
priority routine at the same time, the Master device will be
given priority, and the Slave device will start its routine after the
Master has finished.
Transceiver Interface
The MU9C8148 connects to the received data bus between the
TMS38053/4 and the TMS380CX6. The differential Manchester
INSTRUCTION SET DESCRIPTION
The “Stop Execution” instruction stops the execution of the
routine currently running. Control is transferred to the arbiter.
Instruction:
Binary Op Code: iiii iiii iiii iiii wce0
LANCAM Instruction
i
Instruction Code (see The LANCAM Handbook)
Instruction:
Wait for match for yyyyB + 4 cycles, if no
match then execute at Branch Routine
Address selected.
w
c
e
The state of /W
The state of /CM
The state of /EC
Binary Op Code: 0001 yyyy rrrr rrrr xxx1
y
r
x
Wait period
Reserved (set LOW)
Don't Care
This instruction transfers data or commands to or from the
LANCAM. Instructions from the LANCAM instruction set are
described in the LANCAM Handbook. The state of the control
outputs /W, /CM and /EC at the falling edge of /E for this cycle
are defined by w,c, and e.
This instruction waits for a maximum period of yyyyB + 4 clock
cycles for the /MI input to become active, asserting XMATCH
and XFAIL as appropriate. If no match condition occurs during
that period, a branch is executed to the address stored in the
Branch Routine address determined by the frame type. If a
match condition is detected, execution proceeds to the
instruction at the next address.
Instruction:
Binary Op Code: 0000 0000 0000 0000 xxx1
Don't Care
Stop Execution
x
Rev. 5.5 Draft web
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MUSIC [ MUSIC SEMICONDUCTORS ]
