MU9C1965A/L LANCAM MP
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW. Inputs
should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good layout
and bypassing techniques. Refer to the Electrical Characteristics section for more information.
/E (Chip Enable, Input, TTL)
DQ31–0 (Data Bus, I/O, TTL)
The /E input enables the device while LOW. The falling
edge registers the control signals /W, /CM, /EC. The rising
edge locks the daisy chain, turns off the DQ pins, and clocks
the Destination and Source Segment counters. The four
cycle types enabled by /E are shown in Table 2.
The DQ31–0 lines convey data, commands, and status to
and from the LANCAM MP, as shown in Table 3. /W and
/CM control the direction and nature of the information
that flows to or from the device. When /E is HIGH,
DQ31–0 go to Hi-Z.
/MF (Match Flag, Output, TTL)
The /MF output goes LOW when one or more valid matches
occur during a Compare cycle. /MF becomes valid after /E
goes HIGH on the cycle that enables the daisy chain (on
the first cycle that /EC is registered LOW by the previous
falling edge of /E; see Figure 5 on page 15). In a daisy
chain, valid match(es) in higher priority devices are passed
from the /MI input to /MF. If the daisy chain is enabled but
the match flag is disabled in the Control register, the /MF
output only depends on the /MI input of the device (/MF=
/MI). /MF is HIGH if there is no match or when the daisy
chain is disabled (/E goes HIGH when /EC was HIGH on the
previous falling edge of /E). The System Match flag is the
/MF pin of the last device in the daisy chain. /MF will be
reset when the active configuration register set is changed.
/W
/CM
LOW
HIGH
LOW
HIGH
Cycle Type
LOW
LOW
HIGH
HIGH
Command Write Cycle
Data Write Cycle
Command Read Cycle
Data Read Cycle
Table 2: I/O Cycles
/W (Write Enable, Input, TTL)
The /W input selects the direction of data flow during a
device cycle. /W LOW selects a Write cycle and /W HIGH
selects a Read cycle.
/CM (Data/Command Select, Input, TTL)
The /CM input selects whether the input signals on
DQ31–0 are data or commands. /CM LOW selects Command
cycles and /CM HIGH selects Data cycles.
/EC (Enable Daisy Chain, Input, TTL)
The /EC signal performs two functions. The /EC input
enables the /MF output to show the results of a comparison,
as shown in Figure 5 on page 15. If /EC is LOW at the
falling edge of /E in a given cycle, the /MF output is enabled.
Otherwise, the /MF output is held HIGH. The /EC signal
also enables the /MF–/MI daisy chain, which serves to
select the device with the Highest-Priority Match in a string
of LANCAMs. Tables 6a and 6b on page 12 explain the
effect of the /EC signal on a device with or without a match
in both Standard and Enhanced modes. /EC must be HIGH
during initialization.
NC
/FF
/MI
GND
GND
61
62
63
40
39
38
DQ9
/MF
DQ10
64
65
66
67
68
69
37
36
35
34
33
32
31
30
29
28
/MM
GND
GND
/RESET
VCC
VCC
/E
DQ11
NC
VCC
VCC
TEST 2
NC
70
71
72
73
74
75
76
77
78
79
80
80-Pin TQFP
(Top View)
GND
GND
/W
VCC
DQ12
DQ13
VCC
TEST 1
NC
27
26
25
GND
GND
DQ14
DQ15
DQ31
DQ30
GND
24
23
22
21
DQ16
NC
GND
Pinout Diagram
3
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
