MU9C RCP Family
General Description
GENERAL DESCRIPTION
The MU9C RCP family consists of 4K, 8K, 16K, 24K,
and 32K x 64-bit Routing Co-Processors (RCP’s) with a
32-bit wide data interface and a 32-bit ternary compare
instruction. The device is designed for use in layer 3
switches, routers, and layer 2 switches to provide very
high throughput address translation using tables held in
external RAM. The MU9C RCP has a fully deterministic
search time, independent of the size of the list and the
position of the data in the list. This unique feature
guarantees that the wire speed address recognition does
not impact the latency or induce jitter on the latency of the
global system. Address fields from the packet header are
compared against a list of entries stored in the array. As a
result of the comparison, the MU9C RCP generates an
index that is used to access an external RAM where port
mapping data and other associated information is stored.
A set of control states provides a powerful and flexible
control interface to the MU9C RCP. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MU9C RCP architecture uses direct hardware control
of the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not required.
OPERATIONAL OVERVIEW
The MU9C RCP is designed to act as an address translator
for lookup tables in layer 3 switches, routers, and layer 2
switches. Refer to Figure 2 for a simplified block diagram
of a switch. During normal operation, the controller
extracts the address information from an arriving packet to
form the comparand, which is then compared against the
contents of the MU9C RCP. The MU9C RCP generates an
index that is used to access the data in an external RAM,
which holds the destination port for accessing the network.
The controller reads the data from the RAM and forwards
the packet.
DQ bus data are used as both the comparand and compare
mask bits 63-32. As a result, this instruction matches a DQ
bit of 0 with bit pairs storing both 0 and X, and a DQ bit of
1 matches bit pairs storing both 1 and X.
IPv4 CIDR addresses are prioritized by placing their
ternary-encoded values into the MU9C RCP memory such
that entries with longer netmasks (longer matches) have
higher priority (lower indices). Thus, when the MU9C
RCP performs a ternary comparison, it will return the
index of the longest matching entry. Typically, the system
is initialized by a processor that writes routing table
information into the MU9C RCP. The index at which a
write takes place is driven onto the PA:AA bus, so that
output port data can be written simultaneously into the
external RAM at the correct index.
A unique feature of the MU9C RCP is its ternary
comparison that processes IPv4 CIDR addresses in a
single cycle. The bits of each MU9C RCP word are paired,
such that each pair can contain two binary values (0,1) or
one ternary (0,1,X= "Don't Care") value. A ternary value
uses two bits, pairing bit n from the first 32 bits (31-0)
with bit n+32. When storing a ternary 0 or 1, the value to
be stored is written into bit n (0<=n<=31), and the
complement of the value is written to bit n+32. Thus, a
ternary 0 written to ternary pair 7 would consist of a 0
stored in bit 7 and a 1 stored in bit 39. When storing a
ternary X, 0 is written to both bits in the pair.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit
is set and reset either with an index or an associative
match. Therefore, when a new entry is written to the
database, its Validity bit is set valid.
When a database location is deleted, the Validity bit for
that entry is reset, and the index of the location is driven
onto the Active Address bus. This simple mechanism
allows easy maintenance of the tables in both the database
and the external RAM.
Using bit pairs that are 32 bits apart simplifies the
computation of the pair by a processor. Assume that the
ternary value we wish to store is contained in two 32-bit
processor words. Word A contains the value to be stored
and word M contains a mask value, with a 0 in each
position at which an X is to be stored. The value to be
written to bits 31-0 of the MU9C RCP is (A&M) and the
value to be written to bits 63-32 of the MU9C RCP is
(~A&M).
The MU9C RCP supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
not acceptable, the MU9C RCP is designed to facilitate
external prioritization across multiple devices.
For layer 2 applications, the MAC addresses are processed
in a binary mode, and the MU9C RCP looks for an exact
match. An MU9C RCP can be used to process both MAC
addresses and IPv4 CIDR in the same device.
A special instruction, CMPT DQ, performs the ternary
comparison processing for IPv4 CIDR addresses. The data
on the DQ bus are used directly as both the comparand and
compare mask bits 31-0, and the one's complement of the
2
Rev. 8.04
MUSIC [ MUSIC SEMICONDUCTORS ]
