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ADS-325A 参数 Datasheet PDF下载

ADS-325A图片预览
型号: ADS-325A
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 20MHz的采样A / D转换器 [10-Bit, 20MHz Sampling A/D Converter]
分类和应用: 转换器
文件页数/大小: 8 页 / 145 K
品牌: MURATA-PS [ MURATA POWER SOLUTIONS INC. ]
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®
®
ADS-325A
Re-initiating the Start-up Calibration
The start-up calibration function can be re-initiated at any time
desired after the power and the references are supplied. Apply
a positive pulse to CE pin (pin 24) or a negative pulse to
RESET pin (pin 15). The pulse width of these pulses must be
equal to or wider than one A/D clock cycle. Also due to this
feature, you can make sure of a proper start-up calibration at
power-up by making a C-R delay connection with the RESET
pin as shown in Figure 4c.
Using Start-up Calibration Function Only
Internal and external calibration functions need not be
employed after start-up calibration. To use only the start-up
calibration function, connect the SEL pin (pin 17) to AGND and
the CAL pin (pin 14) to +AV
S
or AGND.
Auto Calibration Function
After the start up calibration is completed, the internal
calibration function can periodically and automatically generate
calibration pulses when the auto calibration mode is enabled.
To enable this function connect the SEL pin (pin 17) and the
CAL pin (pin 41) to +AV
S
. In this mode a 24-bit counter is
counted with every 16 A/D clock cycles and the carry-out is
used as the calibration pulse. The period of the calibration
pulse generated is as follows:
Period of Auto-calibration pulse = 1/f
CLK
x 16 x 16,777,216
For the case when the A/D clock frequency is 14.3MHz, the
calibration pulse generation cycle is 18.8 seconds. Since a
single calibration process is performed once every seven
pulses, the total calibration cycle is approximately
132 seconds.
OUT
+AV
S
14-BIT COUNTER
A/D CLOCK
1/16
CLR
CO
D
Q
CLR
+AV
S
AGND
SENSE
AMP #1
24-BIT COUNTER
CO
CLR
V
RT
V
RB
RESET
CE
SENSE
AMP #2
SEL
CAL
Figure 4a Internal Calibration Pulse Generation Circuit
VOLTS
+5
+AV
S
V
RT
1V
+2.5
V
RB
+AV
S
+AV
S
5V
V
RT
TIME
0
RESET
15
SENSE AMP #1
V
RB
SENSE AMP #2
CLR
RESET = HIGH, CE = LOW
CE = "L"
Figure 4b. Conditions for Start-Up Calibration
Figure 4c. Start-up Calibration using RESET
T
PW1
T
PW0
CLOCK
+1.65V
Tsd
ANALOG
INPUT
N
N+1
N+2
+1.65V (+DV
S
= +3.3V)
+2.5V (+DV
S
= +5.0V)
N+3
T
DL
N+4
OUTPUT
ENABLE (OE)
OUTPUT
DATA
T
PEZ
T
PZE
+1.65V (+DV
S
= +3.3V)
+2.5V (+DV
S
= +5.0V)
OUTPUT
DATA
N–3
N–2
N–1
N
ACTIVE
HIGH IMPEDENCE
ACTIVE
= SAMPLING POINT
+1.65V (+DV
S
= +3.3V)
+2.5V (+DV
S
= +5.0V)
Figure 5. ADS-325A Timing Diagrams
5